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Subversion Repositories fluid_core_2

[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [FluidCore_preroute.twx] - Rev 4

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
                                        twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
                                                           NETDELAY | 
                                                           NETSKEW | 
                                                           PATH |
                                                           DEFPERIOD |
                                                           UNCONSTPATH |
                                                           DEFPATH | 
                                                           PATH2SETUP |
                                                           UNCONSTPATH2SETUP | 
                                                           PATHCLASS | 
                                                           PATHDELAY | 
                                                           PERIOD |
                                                           FREQUENCY |
                                                           PATHBLOCK |
                                                           OFFSET |
                                                           OFFSETIN |
                                                           OFFSETINCLOCK | 
                                                           UNCONSTOFFSETINCLOCK |
                                                           OFFSETINDELAY |
                                                           OFFSETINMOD |
                                                           OFFSETOUT |
                                                           OFFSETOUTCLOCK |
                                                           UNCONSTOFFSETOUTCLOCK | 
                                                           OFFSETOUTDELAY |
                                                           OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
                                           twEndPtCnt?,
                                           twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
                                                twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
                                          fDCMJit CDATA #IMPLIED
                                          fPhaseErr CDATA #IMPLIED
                                          sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
                         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
                                          best CDATA #IMPLIED requested CDATA #IMPLIED
                                          errors CDATA #IMPLIED
                                          score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.5 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
3 -fastpaths -xml FluidCore_preroute.twx FluidCore_map.ncd -o
FluidCore_preroute.twr FluidCore.pcf -ucf Test_Bed.ucf -ucf FluidCore.ucf

</twCmdLine><twDesign>FluidCore_map.ncd</twDesign><twDesignPath>FluidCore_map.ncd</twDesignPath><twPCF>FluidCore.pcf</twPCF><twPcfPath>FluidCore.pcf</twPcfPath><twDevInfo arch="spartan3e" pkg="fg320"><twDevName>xc3s500e</twDevName><twSpeedGrade>-4</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2013-03-26</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3284 - This timing report was generated using estimated delay information.  For accurate numbers, please refer to the post Place and Route timing report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="6">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="7">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation.  Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twConst anchorID="8" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_Clk = PERIOD &quot;Clk&quot; 200 MHz HIGH 50%;" ScopeName="">TS_Clk = PERIOD TIMEGRP &quot;Clk&quot; 200 MHz HIGH 50%;</twConstName><twItemCnt>12461</twItemCnt><twErrCntSetup>1128</twErrCntSetup><twErrCntEndPt>1143</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">15</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1856</twEndPtCnt><twPathErrCnt>10222</twPathErrCnt><twMinPer>10.716</twMinPer></twConstHead><twPathRptBanner iPaths="43" iCriticalPaths="39" sType="EndPoint">Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINA), 43 paths
</twPathRptBanner><twPathRpt anchorID="9"><twConstPath anchorID="10" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.716</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.744</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.F1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_4</twBEL><twBEL>Reg_File_inst/mux29_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.355</twRouteDel><twTotDel>8.744</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.2</twPctLog><twPctRoute>49.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.716</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.744</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_5</twBEL><twBEL>Reg_File_inst/mux29_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.355</twRouteDel><twTotDel>8.744</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.2</twPctLog><twPctRoute>49.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.604</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_2</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.632</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_2</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X36Y62.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X36Y62.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.652</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;1&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G1</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.487</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_5</twBEL><twBEL>Reg_File_inst/mux29_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.449</twLogDel><twRouteDel>4.183</twRouteDel><twTotDel>8.632</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>51.5</twPctLog><twPctRoute>48.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="43" iCriticalPaths="39" sType="EndPoint">Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINB), 43 paths
</twPathRptBanner><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.716</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.744</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y41.F1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y41.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp><twBEL>Reg_File_inst/mux29_51</twBEL><twBEL>Reg_File_inst/mux29_4_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.355</twRouteDel><twTotDel>8.744</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.2</twPctLog><twPctRoute>49.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.716</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.744</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y41.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y41.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp><twBEL>Reg_File_inst/mux29_6</twBEL><twBEL>Reg_File_inst/mux29_4_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.355</twRouteDel><twTotDel>8.744</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.2</twPctLog><twPctRoute>49.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.604</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_2</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_7</twDest><twTotPathDel>8.632</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_2</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_7</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X36Y62.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X36Y62.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.652</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;1&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G1</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.487</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y41.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.207</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y41.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp><twBEL>Reg_File_inst/mux29_6</twBEL><twBEL>Reg_File_inst/mux29_4_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y40.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux29_4_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y40.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;7&gt;</twComp><twBEL>Reg_File_inst/mux29_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_7</twBEL></twPathDel><twLogDel>4.449</twLogDel><twRouteDel>4.183</twRouteDel><twTotDel>8.632</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>51.5</twPctLog><twPctRoute>48.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="43" iCriticalPaths="39" sType="EndPoint">Paths for end point ID_Stage_inst/buff_op_a_18 (SLICE_X64Y52.FXINA), 43 paths
</twPathRptBanner><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.680</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_18</twDest><twTotPathDel>8.708</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_18</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.F1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.171</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_4</twBEL><twBEL>Reg_File_inst/mux9_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux9_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_18</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.319</twRouteDel><twTotDel>8.708</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.4</twPctLog><twPctRoute>49.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.680</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_4</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_18</twDest><twTotPathDel>8.708</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_4</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_18</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X38Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X38Y58.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.592</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G3</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.659</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.171</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_5</twBEL><twBEL>Reg_File_inst/mux9_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux9_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_18</twBEL></twPathDel><twLogDel>4.389</twLogDel><twRouteDel>4.319</twRouteDel><twTotDel>8.708</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>50.4</twPctLog><twPctRoute>49.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-5.568</twSlack><twSrc BELType="FF">IF_ID_reg/pipeline_register_2</twSrc><twDest BELType="LATCH">ID_Stage_inst/buff_op_a_18</twDest><twTotPathDel>8.596</twTotPathDel><twClkSkew dest = "2.137" src = "4.109">1.972</twClkSkew><twDelConst>5.000</twDelConst><twExceeds>1</twExceeds><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>IF_ID_reg/pipeline_register_2</twSrc><twDest BELType='LATCH'>ID_Stage_inst/buff_op_a_18</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X36Y62.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">EX_MEM_reg/Clk_RST</twSrcClk><twPathDel><twSite>SLICE_X36Y62.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.652</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;1&gt;</twComp><twBEL>IF_ID_reg/pipeline_register_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.G1</twSite><twDelType>net</twDelType><twFanCnt>14</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.487</twDelInfo><twComp>IF_ID_reg/pipeline_register&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y63.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.342</twDelInfo><twComp>ID_Stage_inst/rrr_adm_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y63.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>ID_EX_reg/pipeline_register_77_BRB1</twComp><twBEL>ID_Stage_inst/rrr_adm</twBEL></twPathDel><twPathDel><twSite>SLICE_X65Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.147</twDelInfo><twComp>rrr_adm</twComp></twPathDel><twPathDel><twSite>SLICE_X65Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>reg_a&lt;2&gt;</twComp><twBEL>ID_Stage_inst/RF_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.G1</twSite><twDelType>net</twDelType><twFanCnt>128</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.171</twDelInfo><twComp>reg_a&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">1.033</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_5</twBEL><twBEL>Reg_File_inst/mux9_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y52.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>Reg_File_inst/mux9_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y52.CLK</twSite><twDelType>Tfxck</twDelType><twDelInfo twEdge="twRising">0.542</twDelInfo><twComp>ID_Stage_inst/buff_op_a&lt;18&gt;</twComp><twBEL>Reg_File_inst/mux9_2_f6</twBEL><twBEL>ID_Stage_inst/buff_op_a_18</twBEL></twPathDel><twLogDel>4.449</twLogDel><twRouteDel>4.147</twRouteDel><twTotDel>8.596</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twDestClk><twPctLog>51.8</twPctLog><twPctRoute>48.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_Clk = PERIOD TIMEGRP &quot;Clk&quot; 200 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point ID_EX_reg/pipeline_register_69_BRB0 (SLICE_X36Y43.BY), 1 path
</twPathRptBanner><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-0.566</twSlack><twSrc BELType="LATCH">ID_Stage_inst/buff_op_b_7</twSrc><twDest BELType="FF">ID_EX_reg/pipeline_register_69_BRB0</twDest><twTotPathDel>1.406</twTotPathDel><twClkSkew dest = "4.109" src = "2.137">-1.972</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='LATCH'>ID_Stage_inst/buff_op_b_7</twSrc><twDest BELType='FF'>ID_EX_reg/pipeline_register_69_BRB0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X39Y44.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twSrcClk><twPathDel><twSite>SLICE_X39Y44.YQ</twSite><twDelType>Tcklo</twDelType><twDelInfo twEdge="twFalling">0.533</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;7&gt;</twComp><twBEL>ID_Stage_inst/buff_op_b_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y43.BY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.721</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;7&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X36Y43.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.152</twDelInfo><twComp>ID_EX_reg/pipeline_register_45_BRB0</twComp><twBEL>ID_EX_reg/pipeline_register_69_BRB0</twBEL></twPathDel><twLogDel>0.685</twLogDel><twRouteDel>0.721</twRouteDel><twTotDel>1.406</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">EX_MEM_reg/Clk_RST</twDestClk><twPctLog>48.7</twPctLog><twPctRoute>51.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point ID_EX_reg/pipeline_register_61_BRB0 (SLICE_X37Y56.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-0.371</twSlack><twSrc BELType="LATCH">ID_Stage_inst/buff_op_b_15</twSrc><twDest BELType="FF">ID_EX_reg/pipeline_register_61_BRB0</twDest><twTotPathDel>1.601</twTotPathDel><twClkSkew dest = "4.109" src = "2.137">-1.972</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='LATCH'>ID_Stage_inst/buff_op_b_15</twSrc><twDest BELType='FF'>ID_EX_reg/pipeline_register_61_BRB0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X43Y58.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twSrcClk><twPathDel><twSite>SLICE_X43Y58.YQ</twSite><twDelType>Tcklo</twDelType><twDelInfo twEdge="twFalling">0.533</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;15&gt;</twComp><twBEL>ID_Stage_inst/buff_op_b_15</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y56.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.975</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;15&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X37Y56.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.093</twDelInfo><twComp>ID_EX_reg/pipeline_register_61_BRB0</twComp><twBEL>ID_EX_reg/pipeline_register_61_BRB0</twBEL></twPathDel><twLogDel>0.626</twLogDel><twRouteDel>0.975</twRouteDel><twTotDel>1.601</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">EX_MEM_reg/Clk_RST</twDestClk><twPctLog>39.1</twPctLog><twPctRoute>60.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point ID_EX_reg/pipeline_register_53_BRB0 (SLICE_X34Y45.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="31"><twConstPath anchorID="32" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-0.360</twSlack><twSrc BELType="LATCH">ID_Stage_inst/buff_op_b_23</twSrc><twDest BELType="FF">ID_EX_reg/pipeline_register_53_BRB0</twDest><twTotPathDel>1.612</twTotPathDel><twClkSkew dest = "4.109" src = "2.137">-1.972</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='LATCH'>ID_Stage_inst/buff_op_b_23</twSrc><twDest BELType='FF'>ID_EX_reg/pipeline_register_53_BRB0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X35Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="5.000">Clk_IBUF</twSrcClk><twPathDel><twSite>SLICE_X35Y52.YQ</twSite><twDelType>Tcklo</twDelType><twDelInfo twEdge="twFalling">0.533</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;23&gt;</twComp><twBEL>ID_Stage_inst/buff_op_b_23</twBEL></twPathDel><twPathDel><twSite>SLICE_X34Y45.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.945</twDelInfo><twComp>ID_Stage_inst/buff_op_b&lt;23&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X34Y45.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.134</twDelInfo><twComp>ID_EX_reg/pipeline_register_53_BRB0</twComp><twBEL>ID_EX_reg/pipeline_register_53_BRB0</twBEL></twPathDel><twLogDel>0.667</twLogDel><twRouteDel>0.945</twRouteDel><twTotDel>1.612</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">EX_MEM_reg/Clk_RST</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="33"><twPinLimitBanner>Component Switching Limit Checks: TS_Clk = PERIOD TIMEGRP &quot;Clk&quot; 200 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="34" type="MINLOWPULSE" name="Trpw" slack="1.808" period="5.000" constraintValue="2.500" deviceLimit="1.596" physResource="exMemoryAddr&lt;0&gt;/SR" logResource="EX_MEM_reg/pipeline_register_68/SR" locationPin="V15.SR" clockNet="EX_MEM_reg/zero"/><twPinLimit anchorID="35" type="MINHIGHPULSE" name="Trpw" slack="1.808" period="5.000" constraintValue="2.500" deviceLimit="1.596" physResource="exMemoryAddr&lt;0&gt;/SR" logResource="EX_MEM_reg/pipeline_register_68/SR" locationPin="V15.SR" clockNet="EX_MEM_reg/zero"/><twPinLimit anchorID="36" type="MINLOWPULSE" name="Trpw" slack="1.808" period="5.000" constraintValue="2.500" deviceLimit="1.596" physResource="exMemoryAddr&lt;1&gt;/SR" logResource="EX_MEM_reg/pipeline_register_69/SR" locationPin="U15.SR" clockNet="EX_MEM_reg/zero"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="37">1</twUnmetConstCnt><twDataSheet anchorID="38" twNameLen="15"><twClk2SUList anchorID="39" twDestWidth="3"><twDest>Clk</twDest><twClk2SU><twSrc>Clk</twSrc><twRiseRise>10.716</twRiseRise></twClk2SU><twClk2SU><twSrc>RST</twSrc><twRiseRise>10.716</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="40" twDestWidth="3"><twDest>RST</twDest><twClk2SU><twSrc>Clk</twSrc><twRiseRise>8.165</twRiseRise></twClk2SU><twClk2SU><twSrc>RST</twSrc><twRiseRise>8.165</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="41"><twErrCnt>1143</twErrCnt><twScore>2952759</twScore><twSetupScore>2949354</twSetupScore><twHoldScore>3405</twHoldScore><twConstCov><twPathCnt>12461</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>3911</twConnCnt></twConstCov><twStats anchorID="42"><twMinPer>10.716</twMinPer><twFootnote number="1" /><twMaxFreq>93.318</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Mon Apr 27 19:19:28 2015 </twTimestamp></twFoot><twClientInfo anchorID="43"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 143 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

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