Subversion Repositories fluid_core_2

`timescale 1ns / 1ps
`include "Configuration.v"
 
module P_Reg(
		Clk,
		RST,
		bubble,
		stall,
		prev_stage,
		next_stage
    );
 
	parameter p_reg_w = 7;
 
	input Clk, RST, bubble, stall;
	input [0:p_reg_w] prev_stage;
	output [0:p_reg_w] next_stage;
 
	wire zero, Clk_RST;
	assign Clk_RST = Clk || RST;
	assign zero = RST || ~bubble;
 
	reg [0:p_reg_w] pipeline_register;
 
 
	always@(posedge Clk_RST) begin
	if (zero) begin
		pipeline_register <=0;
	end else begin
		if (~stall) pipeline_register <= prev_stage;
	end 
	end
 
	assign next_stage = pipeline_register;
endmodule