Subversion Repositories fluid_core_2

`timescale 1ns / 1ps
`include "Configuration.v"
module Staller(
	input Clk,
	input RST,
	input bubble,
	input load_hazard,
	output stall,
	output [0:4] bubble_lines
    );
 
	reg [0:8] bubble_reg;
	reg stall_reg;
 
		initial begin
			stall_reg <= 0;
		end
 
	wire Clk_RST;
	assign Clk_RST = Clk || RST;
 
	always@(posedge Clk_RST) begin
		if (RST) begin
			bubble_reg <= 9'b111100000;
		end else begin
		  if (bubble) begin
			bubble_reg <= 9'b111100000;
		  end else begin
			bubble_reg <= {1,bubble_reg[0:7]};
		  end
 
		  if (~stall_reg) begin
			if (load_hazard) begin
				stall_reg <= 1;
			end else begin
				stall_reg <= 0;
			end
		   end else begin
				stall_reg <= 0;
			end
		end
	end
 
 
 
	assign bubble_lines = bubble_reg[4:8];
	assign stall = stall_reg;
endmodule