Subversion Repositories fluid_core_2

Release 14.5 - xst P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: Test_Bed.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Test_Bed.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Test_Bed"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : Test_Bed
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : Yes

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : True
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "uOP_Store.v" in library work
Compiling verilog include file "Configuration.v"
Compiling verilog file "int_ALU.v" in library work
Compiling verilog include file "Configuration.v"
Module <uOP_Store> compiled
Compiling verilog file "WB_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <int_ALU> compiled
Compiling verilog file "Staller.v" in library work
Compiling verilog include file "Configuration.v"
Module <WB_Stage> compiled
Compiling verilog file "Reg_Hist.v" in library work
Compiling verilog include file "Configuration.v"
Module <Staller> compiled
Compiling verilog file "Reg_File.v" in library work
Compiling verilog include file "Configuration.v"
Module <Reg_Hist> compiled
Compiling verilog file "P_Reg.v" in library work
Compiling verilog include file "Configuration.v"
Module <Reg_File> compiled
Compiling verilog file "MEM_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <P_Reg> compiled
Compiling verilog file "interrupt_unit.v" in library work
Compiling verilog include file "Configuration.v"
Module <MEM_Stage> compiled
Compiling verilog file "IF_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <interrupt_unit> compiled
Compiling verilog file "ID_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <IF_Stage> compiled
Compiling verilog file "EX_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <ID_Stage> compiled
Compiling verilog file "ioPort.v" in library work
Compiling verilog include file "Configuration.v"
Module <EX_Stage> compiled
Compiling verilog file "Inst_Mem.v" in library work
Compiling verilog include file "Configuration.v"
Compiling verilog include file "Programming.v"
Module <ioPort> compiled
WARNING:HDLCompilers:299 - "Inst_Mem.v" line 15 Too many digits specified in binary constant
Compiling verilog file "FluidCore.v" in library work
Compiling verilog include file "Configuration.v"
Module <Inst_Mem> compiled
Compiling verilog file "data_mem.v" in library work
Compiling verilog include file "Configuration.v"
Module <FluidCore> compiled
Compiling verilog file "Test_Bed.v" in library work
Compiling verilog include file "Configuration.v"
Module <data_mem> compiled
Module <Test_Bed> compiled
No errors in compilation
Analysis of file <"Test_Bed.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <Test_Bed> in library <work>.

Analyzing hierarchy for module <FluidCore> in library <work>.

Analyzing hierarchy for module <Inst_Mem> in library <work>.

Analyzing hierarchy for module <data_mem> in library <work>.

Analyzing hierarchy for module <ioPort> in library <work>.

Analyzing hierarchy for module <Staller> in library <work>.

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000000001111"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000001110101"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000001000111"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000000100110"

Analyzing hierarchy for module <IF_Stage> in library <work>.

Analyzing hierarchy for module <Reg_File> in library <work>.

Analyzing hierarchy for module <Reg_Hist> in library <work>.

Analyzing hierarchy for module <ID_Stage> in library <work>.

Analyzing hierarchy for module <EX_Stage> in library <work>.

Analyzing hierarchy for module <MEM_Stage> in library <work>.

Analyzing hierarchy for module <WB_Stage> in library <work>.

Analyzing hierarchy for module <interrupt_unit> in library <work>.

Analyzing hierarchy for module <uOP_Store> in library <work>.

Analyzing hierarchy for module <int_ALU> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <Test_Bed>.
Module <Test_Bed> is correct for synthesis.
 
Analyzing module <FluidCore> in library <work>.
Module <FluidCore> is correct for synthesis.
 
Analyzing module <Staller> in library <work>.
Module <Staller> is correct for synthesis.
 
Analyzing module <P_Reg.1> in library <work>.
        p_reg_w = 32'sb00000000000000000000000000001111
Module <P_Reg.1> is correct for synthesis.
 
Analyzing module <P_Reg.2> in library <work>.
        p_reg_w = 32'sb00000000000000000000000001110101
Module <P_Reg.2> is correct for synthesis.
 
Analyzing module <P_Reg.3> in library <work>.
        p_reg_w = 32'sb00000000000000000000000001000111
Module <P_Reg.3> is correct for synthesis.
 
Analyzing module <P_Reg.4> in library <work>.
        p_reg_w = 32'sb00000000000000000000000000100110
Module <P_Reg.4> is correct for synthesis.
 
Analyzing module <IF_Stage> in library <work>.
Module <IF_Stage> is correct for synthesis.
 
Analyzing module <Reg_File> in library <work>.
Module <Reg_File> is correct for synthesis.
 
Analyzing module <Reg_Hist> in library <work>.
Module <Reg_Hist> is correct for synthesis.
 
Analyzing module <ID_Stage> in library <work>.
Module <ID_Stage> is correct for synthesis.
 
Analyzing module <uOP_Store> in library <work>.
Module <uOP_Store> is correct for synthesis.
 
Analyzing module <EX_Stage> in library <work>.
Module <EX_Stage> is correct for synthesis.
 
Analyzing module <int_ALU> in library <work>.
Module <int_ALU> is correct for synthesis.
 
Analyzing module <MEM_Stage> in library <work>.
Module <MEM_Stage> is correct for synthesis.
 
Analyzing module <WB_Stage> in library <work>.
Module <WB_Stage> is correct for synthesis.
 
Analyzing module <interrupt_unit> in library <work>.
        Calling function <log2>.
        Calling function <log2>.
INFO:Xst:1607 - Contents of array <isr_vectors> may be accessed with an index that does not cover the full array size.
Module <interrupt_unit> is correct for synthesis.
 
Analyzing module <Inst_Mem> in library <work>.
Module <Inst_Mem> is correct for synthesis.
 
Analyzing module <data_mem> in library <work>.
Module <data_mem> is correct for synthesis.
 
Analyzing module <ioPort> in library <work>.
Module <ioPort> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Inst_Mem>.
    Related source file is "Inst_Mem.v".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <inst_addr<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1781 - Signal <instruction> is used but never assigned. Tied to default value.
WARNING:Xst:1780 - Signal <instb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 13x16-bit ROM for signal <$COND_19>.
    Summary:
        inferred   1 ROM(s).
Unit <Inst_Mem> synthesized.


Synthesizing Unit <data_mem>.
    Related source file is "data_mem.v".
    Found 10x32-bit single-port RAM <Mram_data_bank> for signal <data_bank>.
    Found 32-bit tristate buffer for signal <data>.
    Found 32-bit register for signal <data_buff>.
    Summary:
        inferred   1 RAM(s).
        inferred  32 D-type flip-flop(s).
        inferred  32 Tristate(s).
Unit <data_mem> synthesized.


Synthesizing Unit <ioPort>.
    Related source file is "ioPort.v".
    Found 4-bit tristate buffer for signal <fc_data>.
    Found 4-bit tristate buffer for signal <io_data>.
    Found 4-bit register for signal <io_data_buff>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   8 Tristate(s).
Unit <ioPort> synthesized.


Synthesizing Unit <Staller>.
    Related source file is "Staller.v".
    Found 9-bit register for signal <bubble_reg>.
    Found 1-bit register for signal <stall_reg>.
    Summary:
        inferred  10 D-type flip-flop(s).
Unit <Staller> synthesized.


Synthesizing Unit <P_Reg_1>.
    Related source file is "P_Reg.v".
    Found 16-bit register for signal <pipeline_register>.
    Summary:
        inferred  16 D-type flip-flop(s).
Unit <P_Reg_1> synthesized.


Synthesizing Unit <P_Reg_2>.
    Related source file is "P_Reg.v".
    Found 118-bit register for signal <pipeline_register>.
    Summary:
        inferred 118 D-type flip-flop(s).
Unit <P_Reg_2> synthesized.


Synthesizing Unit <P_Reg_3>.
    Related source file is "P_Reg.v".
    Found 72-bit register for signal <pipeline_register>.
    Summary:
        inferred  72 D-type flip-flop(s).
Unit <P_Reg_3> synthesized.


Synthesizing Unit <P_Reg_4>.
    Related source file is "P_Reg.v".
    Found 39-bit register for signal <pipeline_register>.
    Summary:
        inferred  39 D-type flip-flop(s).
Unit <P_Reg_4> synthesized.


Synthesizing Unit <IF_Stage>.
    Related source file is "IF_Stage.v".
    Found 4-bit tristate buffer for signal <stkFlag>.
    Found 10-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 57.
    Found 6-bit adder carry out for signal <add0000$addsub0000> created at line 44.
    Found 16-bit register for signal <IR>.
    Found 6-bit register for signal <PC>.
    Found 6-bit adder for signal <PC$addsub0000> created at line 51.
    Found 40-bit register for signal <PCStack>.
    Found 2-bit updown counter for signal <PCStackPtr>.
    Found 2-bit adder for signal <PCStackPtr$add0000> created at line 41.
    Summary:
        inferred   1 Counter(s).
        inferred  62 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
        inferred  10 Multiplexer(s).
        inferred   4 Tristate(s).
Unit <IF_Stage> synthesized.


Synthesizing Unit <Reg_File>.
    Related source file is "Reg_File.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 256-bit register for signal <registers>.
INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <registers>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
        inferred 256 D-type flip-flop(s).
        inferred  64 Multiplexer(s).
Unit <Reg_File> synthesized.


Synthesizing Unit <Reg_Hist>.
    Related source file is "Reg_Hist.v".
    Found 1-bit xor2 for signal <reg_src_a_1$xor0000> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_1$xor0001> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_1$xor0002> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0000> created at line 26.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0001> created at line 26.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0002> created at line 26.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0000> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0001> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0002> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0000> created at line 28.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0001> created at line 28.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0002> created at line 28.
    Found 1-bit xor2 for signal <st_src_1$xor0000> created at line 29.
    Found 1-bit xor2 for signal <st_src_1$xor0001> created at line 29.
    Found 1-bit xor2 for signal <st_src_1$xor0002> created at line 29.
    Found 1-bit xor2 for signal <st_src_2$xor0000> created at line 30.
    Found 1-bit xor2 for signal <st_src_2$xor0001> created at line 30.
    Found 1-bit xor2 for signal <st_src_2$xor0002> created at line 30.
Unit <Reg_Hist> synthesized.


Synthesizing Unit <MEM_Stage>.
    Related source file is "MEM_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <ret>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit tristate buffer for signal <ex_mem_data>.
    Found 6-bit tristate buffer for signal <branch_target>.
    Found 1-bit tristate buffer for signal <mem_Clk>.
    Found 1-bit adder for signal <bc$addsub0000>.
    Found 1-bit adder for signal <bc$addsub0001> created at line 52.
    Found 1-bit adder for signal <bc$addsub0002> created at line 55.
    Found 1-bit xor2 for signal <bc$xor0000> created at line 52.
    Summary:
        inferred   3 Adder/Subtractor(s).
        inferred  39 Tristate(s).
Unit <MEM_Stage> synthesized.


Synthesizing Unit <WB_Stage>.
    Related source file is "WB_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit tristate buffer for signal <wb_dst>.
    Found 32-bit tristate buffer for signal <wb_data>.
    Summary:
        inferred  35 Tristate(s).
Unit <WB_Stage> synthesized.


Synthesizing Unit <interrupt_unit>.
    Related source file is "interrupt_unit.v".
    Found 5x6-bit dual-port RAM <Mram_isr_vectors> for signal <isr_vectors>.
WARNING:Xst:737 - Found 2-bit latch for signal <vctr_inx>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 6-bit tristate buffer for signal <vector>.
    Found 4-bit register for signal <masks>.
    Found 1-bit register for signal <temp_unblock>.
    Summary:
        inferred   1 RAM(s).
        inferred   5 D-type flip-flop(s).
        inferred   6 Tristate(s).
Unit <interrupt_unit> synthesized.


Synthesizing Unit <uOP_Store>.
    Related source file is "uOP_Store.v".
WARNING:Xst:647 - Input <uop_vector<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1781 - Signal <uOP_rom> is used but never assigned. Tied to default value.
    Found 24x13-bit ROM for signal <$COND_13>.
    Summary:
        inferred   1 ROM(s).
Unit <uOP_Store> synthesized.


Synthesizing Unit <int_ALU>.
    Related source file is "int_ALU.v".
WARNING:Xst:647 - Input <prev_Flag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 32-bit latch for signal <result_buff>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <C>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <S>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <O>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Z>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit adder carry out for signal <AUX_14$addsub0000> created at line 29.
    Found 32-bit adder carry out for signal <AUX_15$addsub0000> created at line 30.
    Found 1-bit xor4 for signal <O$xor0000> created at line 39.
    Found 32-bit adder for signal <OP1_>.
    Found 32-bit 8-to-1 multiplexer for signal <result_buff$mux0000> created at line 28.
    Found 32-bit xor2 for signal <result_buff$xor0000> created at line 35.
    Summary:
        inferred   5 Adder/Subtractor(s).
        inferred  32 Multiplexer(s).
        inferred   1 Xor(s).
Unit <int_ALU> synthesized.


Synthesizing Unit <ID_Stage>.
    Related source file is "ID_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 32-bit latch for signal <buff_op_a>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <buff_op_b>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Unit <ID_Stage> synthesized.


Synthesizing Unit <EX_Stage>.
    Related source file is "EX_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <OP3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 4-bit tristate buffer for signal <stkFlag>.
    Found 32-bit register for signal <bb_MEM_WB_reg>.
    Found 32-bit tristate buffer for signal <E0>.
    Found 4-bit register for signal <prev_Flag>.
    Summary:
        inferred  36 D-type flip-flop(s).
        inferred  36 Tristate(s).
Unit <EX_Stage> synthesized.


Synthesizing Unit <FluidCore>.
    Related source file is "FluidCore.v".
WARNING:Xst:1780 - Signal <t_IF_ID_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <adm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <FluidCore> synthesized.


Synthesizing Unit <Test_Bed>.
    Related source file is "Test_Bed.v".
WARNING:Xst:1306 - Output <io_port> is never assigned.
Unit <Test_Bed> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 10x32-bit single-port RAM                             : 1
 5x6-bit dual-port RAM                                 : 1
# ROMs                                                 : 2
 13x16-bit ROM                                         : 1
 24x13-bit ROM                                         : 1
# Adders/Subtractors                                   : 11
 1-bit adder                                           : 3
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 32-bit adder carry out                                : 2
 33-bit adder                                          : 2
 6-bit adder                                           : 1
 6-bit adder carry out                                 : 1
# Counters                                             : 1
 2-bit updown counter                                  : 1
# Registers                                            : 26
 1-bit register                                        : 2
 10-bit register                                       : 4
 118-bit register                                      : 1
 16-bit register                                       : 2
 32-bit register                                       : 10
 39-bit register                                       : 1
 4-bit register                                        : 3
 6-bit register                                        : 1
 72-bit register                                       : 1
 9-bit register                                        : 1
# Latches                                              : 9
 1-bit latch                                           : 5
 2-bit latch                                           : 1
 32-bit latch                                          : 3
# Multiplexers                                         : 4
 10-bit 4-to-1 multiplexer                             : 1
 32-bit 8-to-1 multiplexer                             : 3
# Tristates                                            : 12
 1-bit tristate buffer                                 : 1
 3-bit tristate buffer                                 : 1
 32-bit tristate buffer                                : 4
 4-bit tristate buffer                                 : 4
 6-bit tristate buffer                                 : 2
# Xors                                                 : 21
 1-bit xor2                                            : 19
 1-bit xor4                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <pipeline_register_0> of sequential type is unconnected in block <IF_ID_reg>.
WARNING:Xst:2677 - Node <IR_0> of sequential type is unconnected in block <IF_Stage_inst>.
WARNING:Xst:1710 - FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <data_mem>.
INFO:Xst:3231 - The small RAM <Mram_data_bank> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 10-word x 32-bit                    |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <write_en>      | high     |
    |     addrA          | connected to signal <mem_addr>      |          |
    |     diA            | connected to signal <data>          |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <data_mem> synthesized (advanced).

Synthesizing (advanced) Unit <interrupt_unit>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_isr_vectors> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 5-word x 6-bit                      |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <_cmp_eq0000_0> | low      |
    |     addrA          | connected to signal <intr_inx>      |          |
    |     diA            | connected to signal <new_vector>    |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 5-word x 6-bit                      |          |
    |     addrB          | connected to signal <vctr_inx>      |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <interrupt_unit> synthesized (advanced).
WARNING:Xst:2677 - Node <PCStack_3_5> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_4> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_3> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_2> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_1> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_0> of sequential type is unconnected in block <IF_Stage>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 10x32-bit single-port distributed RAM                 : 1
 5x6-bit dual-port distributed RAM                     : 1
# ROMs                                                 : 2
 13x16-bit ROM                                         : 1
 24x13-bit ROM                                         : 1
# Adders/Subtractors                                   : 11
 1-bit adder                                           : 3
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 32-bit adder carry out                                : 2
 33-bit adder                                          : 2
 6-bit adder                                           : 1
 6-bit adder carry out                                 : 1
# Counters                                             : 1
 2-bit updown counter                                  : 1
# Registers                                            : 644
 Flip-Flops                                            : 644
# Latches                                              : 9
 1-bit latch                                           : 5
 2-bit latch                                           : 1
 32-bit latch                                          : 3
# Multiplexers                                         : 69
 1-bit 4-to-1 multiplexer                              : 4
 1-bit 8-to-1 multiplexer                              : 64
 32-bit 8-to-1 multiplexer                             : 1
# Xors                                                 : 21
 1-bit xor2                                            : 19
 1-bit xor4                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<0>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_0>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_0>
   Signal <MemoryData<0>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<1>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_1>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_1>
   Signal <MemoryData<1>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<2>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_2>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_2>
   Signal <MemoryData<2>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<3>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_3>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_3>
   Signal <MemoryData<3>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<4>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_4>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_4>
   Signal <MemoryData<4>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<5>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_5>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_5>
   Signal <MemoryData<5>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<6>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_6>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_6>
   Signal <MemoryData<6>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<7>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_7>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_7>
   Signal <MemoryData<7>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<8>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_8>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_8>
   Signal <MemoryData<8>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<9>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_9>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_9>
   Signal <MemoryData<9>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<10>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_10>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_10>
   Signal <MemoryData<10>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<11>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_11>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_11>
   Signal <MemoryData<11>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<12>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_12>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_12>
   Signal <MemoryData<12>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<13>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_13>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_13>
   Signal <MemoryData<13>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<14>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_14>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_14>
   Signal <MemoryData<14>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<15>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_15>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_15>
   Signal <MemoryData<15>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<16>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_16>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_16>
   Signal <MemoryData<16>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<17>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_17>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_17>
   Signal <MemoryData<17>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<18>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_18>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_18>
   Signal <MemoryData<18>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<19>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_19>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_19>
   Signal <MemoryData<19>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<20>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_20>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_20>
   Signal <MemoryData<20>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<21>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_21>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_21>
   Signal <MemoryData<21>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<22>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_22>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_22>
   Signal <MemoryData<22>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<23>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_23>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_23>
   Signal <MemoryData<23>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<24>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_24>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_24>
   Signal <MemoryData<24>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<25>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_25>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_25>
   Signal <MemoryData<25>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<26>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_26>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_26>
   Signal <MemoryData<26>> in Unit <Test_Bed> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Test_Bed> on signal <data<27>>; this signal is connected to multiple drivers.
Drivers are: 
   Output signal of BUFT instance <FC_inst/MEM_Stage_inst/ex_mem_data_E0_27>
   Output signal of BUFT instance <data_mem_inst/data_data_buff_27>
   Signal <MemoryData<27>> in Unit <Test_Bed> is assigned to GND


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.98 secs
 
--> 

Total memory usage is 198948 kilobytes

Number of errors   :   28 (   0 filtered)
Number of warnings :   45 (   0 filtered)
Number of infos    :    5 (   0 filtered)