URL
https://opencores.org/ocsvn/fluid_core_2/fluid_core_2/trunk
Subversion Repositories fluid_core_2
[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [Test_Bed.v] - Rev 4
Compare with Previous | Blame | View Log
`timescale 1ns / 1ps `include "Configuration.v" module Test_Bed( input Clk, input RST, input [0:`intr_msb] Interrupt, output [0:`dpw] data, output reg [0:`dpw] io_port ); wire [0:`inst_w] exInstruction; wire [0:`pc_w] exInstAddr; wire MemoryClk, MemoryWrite; wire [0:`memory_bus_w] MemoryAddr; wire [0:`dpw] MemoryData; assign data = MemoryData; FluidCore FC_inst( .Clk (Clk), .RST (RST), .Interrupt(Interrupt), .exInstruction(exInstruction), .exInstAddr(exInstAddr), .exMemoryData(MemoryData), .exMemoryClk(MemoryClk), .exMemoryAddr(MemoryAddr), .exMemoryWrite(MemoryWrite) ); Inst_Mem Inst_Mem_inst ( .Clk (Clk), .inst(exInstruction), .inst_addr(exInstAddr) ); data_mem data_mem_inst( .Clk(MemoryClk), .mem_addr(MemoryAddr), .data(MemoryData), .write_en(MemoryWrite), .en(~MemoryAddr[0]) ); ioPort ioPort_inst( .Clk(MemoryClk), .en(MemoryAddr[0]), .wr(MemoryAddr[3]), .rd(~MemoryAddr[3]), .fc_data(MemoryData) ); endmodule