Subversion Repositories fluid_core_2

ISim log file
Running: C:\Users\Azmath\Documents\M Tech Project\FC2\tb_Test_Bed_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed_isim_beh.wdb 
ISim P.58f (signature 0x7708f090)
This is a Full version of ISim.
WARNING:  For instance FC_inst/MEM_WB_reg/, width 1 of formal port stall is not equal to width 32 of actual constant.
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 40.  For instance FC_inst/Reg_File_inst/, width 3 of formal port wb_reg is not equal to width 5 of actual signal wb_dst.
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 38.  For instance FC_inst/uOP_Store_inst/, width 13 of formal port write_uop is not equal to width 32 of actual signal wb_data.
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 40.  For instance FC_inst/interrupt_unit_inst/, width 3 of formal port intr_inx is not equal to width 5 of actual signal wb_dst.
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 38.  For instance FC_inst/interrupt_unit_inst/, width 6 of formal port new_vector is not equal to width 32 of actual signal wb_data.
WARNING: File "C:/Users/Azmath/Documents/M Tech Project/FC2/Test_Bed.v" Line 16.  For instance uut/ioPort_inst/, width 4 of formal port fc_data is not equal to width 32 of actual signal MemoryData.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# restart
# restart
# run 2.00us
Simulator is doing circuit initialization process.
Finished circuit initialization process.