OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [hibi_udp/] [1.0/] [hibi_udp.1.0.xml] - Rev 160

Go to most recent revision | Compare with Previous | Blame | View Log

<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 09.01.2013 -->
<!-- Time: 13:57:58 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
        <spirit:vendor>TUT</spirit:vendor>
        <spirit:library>ip.hwp.interface</spirit:library>
        <spirit:name>hibi_udp</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:busInterfaces>
                <spirit:busInterface>
                        <spirit:name>clk_udp</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>clk_udp</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>hibi_master</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>AV</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_av_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>COMM</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_comm_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>DATA</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_data_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>RE</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_re_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>WE</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_we_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>hibi_slave</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>AV</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_av_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>COMM</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_comm_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>DATA</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_data_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>EMPTY</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_empty_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>FULL</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>hibi_full_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>clk</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>clk</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>DM9000A</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a.absDef" spirit:version="1.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_chip_sel_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_chip_sel_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_clk_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_clk_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_cmd_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_cmd_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_data_inout</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>15</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_data_inout</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>15</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_interrupt_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_interrupt_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_read_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_read_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_reset_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_reset_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>eth_write_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>eth_write_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>rst_n</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>RESETn</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>rst_n</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
        </spirit:busInterfaces>
        <spirit:model>
                <spirit:views>
                        <spirit:view>
                                <spirit:name>structural</spirit:name>
                                <spirit:envIdentifier>::</spirit:envIdentifier>
                                <spirit:hierarchyRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="hibi_udp.designcfg" spirit:version="1.0"/>
                                <spirit:vendorExtensions>
                                        <kactus2:topLevelViewRef>structural_vhd</kactus2:topLevelViewRef>
                                </spirit:vendorExtensions>
                        </spirit:view>
                        <spirit:view>
                                <spirit:name>structural_vhd</spirit:name>
                                <spirit:envIdentifier>VHDL:Kactus2:</spirit:envIdentifier>
                                <spirit:language spirit:strict="false">vhdl</spirit:language>
                                <spirit:modelName>hibi_udp(structural)</spirit:modelName>
                                <spirit:fileSetRef>
                                        <spirit:localName>structural_vhdlSource</spirit:localName>
                                </spirit:fileSetRef>
                        </spirit:view>
                </spirit:views>
                <spirit:ports>
                        <spirit:port>
                                <spirit:name>clk</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>clk_udp</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_av_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_comm_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>4</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_data_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>31</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_re_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_we_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_av_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_comm_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>4</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_data_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>31</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_empty_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>hibi_full_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                        <spirit:wireTypeDefs>
                                                <spirit:wireTypeDef>
                                                        <spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
                                                        <spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
                                                        <spirit:viewNameRef>rtl</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural</spirit:viewNameRef>
                                                        <spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
                                                </spirit:wireTypeDef>
                                        </spirit:wireTypeDefs>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_chip_sel_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_clk_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_cmd_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_data_inout</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>inout</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>15</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_interrupt_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_read_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_reset_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>eth_write_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>rst_n</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>0</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                </spirit:ports>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>structural_vhdlSource</spirit:name>
                        <spirit:group>sourceFiles</spirit:group>
                        <spirit:file>
                                <spirit:name>vhd/hibi_udp.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:buildCommand>
                                        <spirit:command>vcom</spirit:command>
                                        <spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
                                        <spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
                                </spirit:buildCommand>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
                                <spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource-87</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
                                <spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource-93</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
                                <spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>IP</kactus2:kts_productHier>
                                <kactus2:kts_implementation>HW</kactus2:kts_implementation>
                                <kactus2:kts_firmness>Parameterizable</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.