OpenCores

URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [Makefrag] - Rev 2

Compare with Previous | Blame | View Log

rv32mi_sc_tests =    \
        breakpoint \
        ma_fetch \
        ma_addr \
        scall \
        sbreak \
        shamt \
        csr \
        mcsr \
        illegal

ifeq ($(RISCV_TARGET),riscvOVPsim)
    rv32mi_sc_tests := $(subst breakpoint,,$(rv32mi_sc_tests))
endif

rv32mi_tests = $(addsuffix .elf, $(rv32mi_sc_tests))

target32_tests += $(rv32mi_tests)

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.