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[/] [graphicsaccelerator/] [trunk/] [VGA_Top_map.mrp] - Rev 2
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Release 13.1 Map O.40d (lin)Xilinx Mapping Report File for Design 'VGA_Top'Design Information------------------Command Line : map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off-c 100 -o VGA_Top_map.ncd VGA_Top.ngd VGA_Top.pcfTarget Device : xc3s200Target Package : ft256Target Speed : -5Mapper Version : spartan3 -- $Revision: 1.55 $Mapped Date : Tue May 17 19:21:57 2011Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:Number of Slice Flip Flops: 237 out of 3,840 6%Number of 4 input LUTs: 852 out of 3,840 22%Logic Distribution:Number of occupied Slices: 504 out of 1,920 26%Number of Slices containing only related logic: 504 out of 504 100%Number of Slices containing unrelated logic: 0 out of 504 0%*See NOTES below for an explanation of the effects of unrelated logic.Total Number of 4 input LUTs: 936 out of 3,840 24%Number used as logic: 852Number used as a route-thru: 84The Slice Logic Distribution report is not meaningful if the design isover-mapped for a non-slice resource or if Placement fails.Number of bonded IOBs: 29 out of 173 16%Number of RAMB16s: 6 out of 12 50%Number of BUFGMUXs: 2 out of 8 25%Average Fanout of Non-Clock Nets: 2.90Peak Memory Usage: 140 MBTotal REAL time to MAP completion: 4 secsTotal CPU time to MAP completion: 3 secsNOTES:Related logic is defined as being logic that shares connectivity - e.g. twoLUTs are "related" if they share common inputs. When assembling slices,Map gives priority to combine logic that is related. Doing so results inthe best timing performance.Unrelated logic shares no connectivity. Map will only begin packingunrelated logic into a slice once 99% of the slices are occupied throughrelated logic packing.Note that once logic distribution reaches the 99% level through relatedlogic packing, this does not mean the device is completely utilized.Unrelated logic packing will then begin, continuing until all usable LUTsand FFs are occupied. Depending on your timing budget, increased levels ofunrelated logic packing may adversely affect the overall timing performanceof your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Timing ReportSection 11 - Configuration String InformationSection 12 - Control Set InformationSection 13 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs.Section 4 - Removed Logic Summary---------------------------------2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set thedetailed map report option and rerun map.Section 6 - IOB Properties--------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Term | Strength | Rate | | | Delay |+---------------------------------------------------------------------------------------------------------------------------------------------------------+| B | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Clk | IOB | INPUT | LVCMOS25 | | | | | | || Enables<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Enables<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Enables<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Enables<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || G | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || HS | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || LED | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || MoveDown | IOB | INPUT | LVCMOS25 | | | | | | || MoveLeft | IOB | INPUT | LVCMOS25 | | | | | | || MoveP1 | IOB | INPUT | LVCMOS25 | | | | | | || MoveP2 | IOB | INPUT | LVCMOS25 | | | | | | || MoveRight | IOB | INPUT | LVCMOS25 | | | | | | || MoveUp | IOB | INPUT | LVCMOS25 | | | | | | || R | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || Segments<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || VS | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || button | IOB | INPUT | LVCMOS25 | | | | | | || inColor<0> | IOB | INPUT | LVCMOS25 | | | | | | || inColor<1> | IOB | INPUT | LVCMOS25 | | | | | | || inColor<2> | IOB | INPUT | LVCMOS25 | | | | | | || reset | IOB | INPUT | LVCMOS25 | | | | | | |+---------------------------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Timing Report--------------------------This design was not run using timing mode.Section 11 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 12 - Control Set Information------------------------------------No control set information for this architecture.Section 13 - Utilization by Hierarchy-------------------------------------Use the "-detail" map option to print out the Utilization by Hierarchy section.