Subversion Repositories ha1588

###################################################################
##
## Name     : ha1588_axi_v2_1_0.mpd
## Desc     : Microprocessor Peripheral Description
##
###################################################################

BEGIN ha1588_axi 

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = MIX
OPTION DESC = HA1588
OPTION LONG_DESC = HARDWARE ASSISTED IEEE 1588 IP CORE
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = TRUE


## S_AXI_REG Bus Interfaces
BUS_INTERFACE BUS = S_AXI_REG, BUS_STD = AXI, BUS_TYPE = SLAVE

## S_AXI_REG Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_REG_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI_REG
PARAMETER C_S_AXI_REG_NUM_ADDR_RANGES = 1, BUS = S_AXI_REG, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_S_AXI_REG_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG00_HIGHADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_REG_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG00_BASEADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_S_AXI_REG_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG01_HIGHADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_REG_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG01_BASEADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_S_AXI_REG_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG02_HIGHADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_REG_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG02_BASEADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_S_AXI_REG_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_REG_RNG03_HIGHADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_REG_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI_REG, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_REG_RNG03_BASEADDR, ISVALID = (C_S_AXI_REG_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL

## S_AXI_REG Ports
PORT S_AXI_REG_ACLK = "", BUS = S_AXI_REG, DIR = I, SIGIS = CLK
PORT S_AXI_REG_ARESETN = ARESETN, BUS = S_AXI_REG, DIR = I, SIGIS = RST
PORT S_AXI_REG_AWADDR = AWADDR, BUS = S_AXI_REG, DIR = I, VEC = [(C_S_AXI_REG_ADDR_WIDTH-1):0]
PORT S_AXI_REG_AWPROT = AWPROT, BUS = S_AXI_REG, DIR = I, VEC = [2:0]
PORT S_AXI_REG_AWVALID = AWVALID, BUS = S_AXI_REG, DIR = I
PORT S_AXI_REG_AWREADY = AWREADY, BUS = S_AXI_REG, DIR = O
PORT S_AXI_REG_WDATA = WDATA, BUS = S_AXI_REG, DIR = I, VEC = [(C_S_AXI_REG_DATA_WIDTH-1):0]
PORT S_AXI_REG_WSTRB = WSTRB, BUS = S_AXI_REG, DIR = I, VEC = [((C_S_AXI_REG_DATA_WIDTH/8) -1):0]
PORT S_AXI_REG_WVALID = WVALID, BUS = S_AXI_REG, DIR = I
PORT S_AXI_REG_WREADY = WREADY, BUS = S_AXI_REG, DIR = O
PORT S_AXI_REG_BRESP = BRESP, BUS = S_AXI_REG, DIR = O, VEC = [1:0]
PORT S_AXI_REG_BVALID = BVALID, BUS = S_AXI_REG, DIR = O
PORT S_AXI_REG_BREADY = BREADY, BUS = S_AXI_REG, DIR = I
PORT S_AXI_REG_ARADDR = ARADDR, BUS = S_AXI_REG, DIR = I, VEC = [(C_S_AXI_REG_ADDR_WIDTH-1):0
PORT S_AXI_REG_ARPROT = ARPROT, BUS = S_AXI_REG, DIR = I, VEC = [2:0]
PORT S_AXI_REG_ARVALID = ARVALID, BUS = S_AXI_REG, DIR = I
PORT S_AXI_REG_ARREADY = ARREADY, BUS = S_AXI_REG, DIR = O
PORT S_AXI_REG_RDATA = RDATA, BUS = S_AXI_REG, DIR = O, VEC = [(C_S_AXI_REG_DATA_WIDTH-1):0]
PORT S_AXI_REG_RRESP = RRESP, BUS = S_AXI_REG, DIR = O, VEC = [1:0]
PORT S_AXI_REG_RVALID = RVALID, BUS = S_AXI_REG, DIR = O
PORT S_AXI_REG_RREADY = RREADY, BUS = S_AXI_REG, DIR = I


## EXTERNAL Ports
PORT INTR_OUT  ="", DIR = O, SIGIS = INTERRUPT, SENSITIVITY=LEVEL_HIGH

PORT rtc_clk          = "", DIR = I, SIGIS = CLK
PORT rtc_time_ptp_ns  = "", DIR = O, VEC = [31:0]
PORT rtc_time_ptp_sec = "", DIR = O, VEC = [47:0]
PORT rtc_time_one_pps = "", DIR = O

PORT rx_gmii_clk  = "", DIR = I
PORT rx_gmii_ctrl = "", DIR = I
PORT rx_gmii_data = "", DIR = I, VEC = [ 7:0]
PORT rx_giga_mode = "", DIR = I
PORT tx_gmii_clk  = "", DIR = I
PORT tx_gmii_ctrl = "", DIR = I
PORT tx_gmii_data = "", DIR = I, VEC = [ 7:0]
PORT tx_giga_mode = "", DIR = I

END