Subversion Repositories hdlc

HDLC controller initial features:

1. 8 bit parallel backend interface
2. use external RX and TX clocks
3. Start and end of frame pattern generation
4. Start and end of frame pattern checking
5. Idle pattern generation and detection (all ones)
5. a)  Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
6. Zero insertion 
7. Abort pattern generation and checking
8. Address insertion and detection by software
9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
10. FIFO buffers and synchronization (External)
11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
12. Q.921 compliant(???)