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-------------------------------------------------------------------------------
-- Title      : Hierarchical parametrized block for calculation of sum of
--              multiple values
-- Project    : 
-------------------------------------------------------------------------------
-- File       : tree_adder.vhd
-- Author     : Wojciech M. Zabolotny ( wzab01<at>gmail.com )
-- Company    :
-- License    : BSD
-- Created    : 2013-11-01
-- Last update: 2015-09-23
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2014 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2013-11-01  1.0      WZab    Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
use IEEE.NUMERIC_STD.all;
library work;
use work.lateq_pkg.all;
use work.ex1_pkg.all;
use work.ex1_trees_pkg.all;
 
entity tree_adder is
  generic(
    N_OF_ALL_INS : integer
    );
  port (
    dins  : in  T_USER_DATA_SET(0 to N_OF_ALL_INS-1);
    dout  : out T_USER_DATA_MRK;
    clk   : in  std_logic;
    rst_p : in  std_logic
    );
end tree_adder;
 
architecture beh of tree_adder is
 
  constant N_OF_LEVELS : integer := ex1_nof_stages(N_OF_ALL_INS, EX1_NOF_INS_IN_ADD);
 
  -- Due to VHDL limitations, we have to declare the array of signals
  -- consisiting of N_OF_LEVELS * MF_NOF_INPUTS elements.
  -- Most of them will be removed by the synthesis tools.
  constant C_N_OF_INS_1ST_STAGE : integer             := (EX1_NOF_INS_IN_ADD**N_OF_LEVELS);
  type T_ADD_INTERNAL_DATUM is array (0 to C_N_OF_INS_1ST_STAGE-1) of T_USER_DATA_MRK;
  type T_ADD_INTERNAL_DATA is array (0 to N_OF_LEVELS) of T_ADD_INTERNAL_DATUM;
  signal add_internal_data      : T_ADD_INTERNAL_DATA := (others => (others => C_USER_DATA_MRK_INIT));
 
begin
 
  -- Here we generate tree of adders
  g1 : for i in 0 to n_of_levels-1 generate
    -- level 0 is the output level
    g2 : for j in 0 to (EX1_NOF_INS_IN_ADD**i)-1 generate
      signal data_in : T_EX1_ADD_INS := (others => C_USER_DATA_MRK_INIT);
    begin
      g3 : for k in 0 to EX1_NOF_INS_IN_ADD-1 generate
        --assert false report "indices:" & integer'image(i) & "," & integer'image(j) & "," & integer'image(k) severity note;
        data_in(k) <= add_internal_data(i+1)(j*EX1_NOF_INS_IN_ADD+k);
      end generate g3;
      tree_adder_1st_1 : entity work.tree_adder_1st
        port map (
          dins  => data_in,
          dout  => add_internal_data(i)(j),
          clk   => clk,
          rst_p => rst_p);
    end generate g2;
  end generate g1;
 
  -- Process connecting the inputs
  process (dins) is
  begin  -- process
    for i in 0 to N_OF_ALL_INS-1 loop
      add_internal_data(n_of_levels)(i) <= dins(i);
    end loop;  -- i
  end process;
  dout <= add_internal_data(0)(0);
end beh;