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https://opencores.org/ocsvn/mips_16/mips_16/trunk
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[/] [mips_16/] [trunk/] [bench/] [ID_stage/] [ID_stage_tb_0.do] - Rev 2
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vlib workvlog +incdir+../rtl ../rtl/ID_stage.vvlog +incdir+../rtl ../bench/ID_stage/ID_stage_tb_0.vvsim -t 1ps -novopt -lib work ID_stage_tb_0_vview waveadd wave *add wave /ID_stage_tb_0_v/uut/instruction_regview structureview signalsrun -all