Subversion Repositories mips_enhanced

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/rstn
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/holdn
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbsi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ahbso
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/rfi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/rfo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/crami
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/cramo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/tbi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/tbo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/fpi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/fpo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/cpi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/cpo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/irqi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/irqo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/dbgi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/dbgo
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/iack_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/hclk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/sclk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/hclken
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ici
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/ico
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/dci
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/dco
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/holdnx
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/pholdn
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/muli
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mulo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/divi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/divo
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/din
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/zz_ins_i
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/rst
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/qa
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/qb
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/alu_ur
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/iset
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/dset
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/dmem_data_ur
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/dmem_ctl_ur
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/zz_pc_o1
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/zz_pc_o2
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/iack_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/size
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/rdaddra_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/rdaddrb_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/wb_we_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/wb_addr_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/wb_din_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/iflush
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/iflushl
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/ifline
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/dflush
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/dflushl
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/read1
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/read2
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/hold
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/inull
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/asi
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/nullify
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/esu
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/msu
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/intack
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/fbranch
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/rbranch
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/eenaddr
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/dmds
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/imds
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/eaddr
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/asi_code
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/idata
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/ddata
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/fbranch1
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/zz_pc
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/dmem_ctl_ur1
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rst
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/zz_ins_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/zz_ins_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dout
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/qa
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/qb
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/zz_pc_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iack_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/cop_addr_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dmem_ctl_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/alu_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dmem_data_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/wb_din_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rdaddra_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rdaddrb_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/wb_addr_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/wb_we_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/size
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/branch
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/hold
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/imds
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/dmds
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/asi_pass2
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/pc_next
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/load
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/load_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/rt_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET1375
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET1572
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET1606
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET1640
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET21531
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET457
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/NET767
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS109
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS1158
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS117
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS1196
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS15471
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS1724
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS1726
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS18211
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS197
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS2140
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS2156
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS22401
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS24839
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS27031
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS271
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS28013
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS371
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS422
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS5832
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS5840
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS5993
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS6275
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7101
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7117
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7160
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7219
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7231
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS748
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS756
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS775
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7772
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS7780
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/BUS9884
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/asi_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/asi_pass1
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rst_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/cmp_ctl_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/ext_ctl_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/fw_alu_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/fw_cmp_rs
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/fw_cmp_rt
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/fw_mem_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/id_cmd
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/ins_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/pc_gen_ctl
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/pc_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rd_sel_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/wb_din_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/zz_spc_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/qa
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/qb
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/iack_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/id2ra_ctl_clr_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/id2ra_ctl_cls_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/ra2ex_ctl_clr_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/ext_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/pc_next
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rd_index_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rs_n_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rs_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rt_n_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rt_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rdaddra_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/rdaddrb_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/branch
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/hold
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/NET6609
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/NET6658
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/NET7774
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/NET904
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS1013
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS2085
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS3236
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS3237
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS5421
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS6061
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/BUS6095
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/CLK_NO
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iRF_stage/INS_NO
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rst
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/spc_cls_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/alu_func
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/dmem_fw_ctl
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/ext_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/fw_alu
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/fw_dmem
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxa_ctl_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxa_fw_ctl
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxb_ctl_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/muxb_fw_ctl
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/pc_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rs_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/rt_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/alu_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/dmem_data_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/zz_spc_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/hold
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS2332
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS2446
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS468
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iexec_stage/BUS476
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/load
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/rt1
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/load_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/id2ra_ctl_clr
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/id2ra_ctl_cls
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ra2ex_ctl_clr
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ins_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/alu_func_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/alu_we_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/cmp_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/dmem_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/dmem_ctl_ur_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/ext_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/fsm_dly
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/muxa_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/muxb_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/pc_gen_ctl_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/rd_sel_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/wb_mux_ctl_o
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/wb_we_o
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/size
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/hold
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/asi
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2040
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2048
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2056
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2064
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2072
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2086
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2094
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2102
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2110
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2118
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/decoder_pipe/BUS2126
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_we
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/clk
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/mem_We
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/fw_alu_rn
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/fw_mem_rn
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/rns_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/rnt_i
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_rs_fw
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/alu_rt_fw
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/cmp_rs_fw
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/cmp_rt_fw
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/dmem_fw
add wave -noupdate -format Logic /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/hold
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS1345
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS82
add wave -noupdate -format Literal /testbench/cpu/l3/cpu__0/u0/p0/mips/e1/iforward/BUS937
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {4999998984 ps} {5000000267 ps}