Subversion Repositories myhdl_lfsr

from myhdl import *
from lfsr_tap_table import *
from lfsr_logic import *
import random
 
#Author: Shawn Rainey 
#        rainey.shawn@gmail.com
 
def lfsr_export(exportfn=toVerilog, directory=".", width=32, init_value=1):
 
    reset = ResetSignal(0, active=1, async=True)
    clock = Signal(bool(0))
    word_sig = Signal(modbv(0)[width:])
 
    lfsr_mod = get_lfsr(width, init_value)
 
    exportfn.name = "lfsr_" + str(width)
    exportfn.directory = directory
    exportfn(lfsr_mod, reset, clock, word_sig)
 
def lfsr_sim(clocks, width=32, init_value = 1):
 
    lfsr_mod = get_lfsr(width, init_value)
 
    def lfsr_tb():
        reset = ResetSignal(0, active=1, async=True)
        clock = Signal(bool(0))
        word_sig = Signal(modbv(0)[width:])
 
 
        lfsr_inst = lfsr_mod(reset, clock, word_sig)
 
        @always(delay(1))
        def clock_toggle():
            clock.next = not clock
 
        return instances()
 
    tb = traceSignals(lfsr_tb)
    sim = Simulation(tb)
    sim.run(clocks*2)
 
 
def generate_all_widths():
    lfsr_start = 1
    for width in lfsr_tap_table:
        lfsr_width = width
        if lfsr_width > 2:
            lfsr_start = random.getrandbits(lfsr_width-2)+1
        else:
            lfsr_start = 1
 
        lfsr_export(toVHDL, "generated", lfsr_width, lfsr_start)
        #alternatively: But this has problems with large widths
        #lfsr_export(toVHDL, lfsr_width, lfsr_start)
 
 
if __name__ == "__main__":
    lfsr_width = 32
 
    #start with a pseudo-random number that will fit in our register and be non-zero
    lfsr_start = random.getrandbits(lfsr_width-2)+1
 
    #may also start with a non-zero constant:
    #lfsr_start = 1
 
 
    generate_all_widths()
 
    lfsr_width = 8
    lfsr_start = 1
    #Generate a simulation with 256 clocks
    #lfsr_sim(256, lfsr_width, lfsr_start)