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-- File: generated/lfsr_384.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_384 is
    port (
        reset: in std_logic;
        clock: in std_logic;
        lfsr_out: out unsigned(383 downto 0)
    );
end entity lfsr_384;
 
 
architecture MyHDL of lfsr_384 is
 
 
 
 
 
signal reg_internal: unsigned(383 downto 0);
 
begin
 
 
 
 
 
LFSR_384_LFSR_LOGIC: process (clock, reset) is
begin
    if (reset = '1') then
        reg_internal <= unsigned'"001100011111001101101111110100001001110101011011011111110010111001100100110100011101100010000000100111101011010110100101011100101110001100110101100011101010000100010100110000010010010001011101011010010111110101000010000101010111101110101101010011101110100100000101010101010011111111001011011111001001011100010100101111100111001101110110010001110101111110111100011001111111101111101111";
    elsif rising_edge(clock) then
        if (reg_internal(0) = '1') then
            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000100000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
        else
            reg_internal <= shift_right(reg_internal, 1);
        end if;
    end if;
end process LFSR_384_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;