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// File: generated/lfsr_47.v // Generated by MyHDL 0.9.0 // Date: Thu Jan 11 17:13:37 2018 `timescale 1ns/10ps module lfsr_47 ( reset, clock, out ); input reset; input clock; output [46:0] out; wire [46:0] out; reg [46:0] reg_internal; always @(posedge clock, posedge reset) begin: LFSR_47_LFSR_LOGIC if (reset == 1) begin reg_internal <= 23173814600026; end else begin if ((reg_internal[0] == 1)) begin reg_internal <= ((reg_internal >>> 1) ^ 48'h420000000000); end else begin reg_internal <= (reg_internal >>> 1); end end end assign out = reg_internal; endmodule