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https://opencores.org/ocsvn/natalius_8bit_risc/natalius_8bit_risc/trunk
Subversion Repositories natalius_8bit_risc
[/] [natalius_8bit_risc/] [trunk/] [impl_prj/] [_xmsgs/] [pn_parser.xmsgs] - Rev 13
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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generated --><!-- by the Xilinx ISE software. Any direct editing or --><!-- changes made to this file may result in unpredictable --><!-- behavior or data corruption. It is strongly advised that --><!-- users do not edit the contents of this file. --><!-- --><!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --><messages><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/ALU.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/LIFO.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/control_unit.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/data_path.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/instruction_memory.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/natalius_processor.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/regfile.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1677" ><arg fmt="%s" index="1">Analyzing Verilog file \"C:/natalius/processor_core/shiftbyte.v\" into library work</arg></msg></messages>