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# VeriFLA Logic Analyzer Project File

# Serial port
# On Windows this would be COM5 or similar
#/dev/ttyUSB0
LA.portName=/dev/ttyUSB0
LA.baudRate=115200

# Memory
# ====
LA.memWords=128
# Data input width and indentical samples bits (clones) must be multiple of 8.
LA.dataWordLenBits=8
LA.clonesWordLenBits=8
LA.triggerMatchMemAddr=8


# Generated verilog
# ====
LA.timescaleUnit=1ns
LA.timescalePrecision=10ps
# clockPeriod expressed in [timescaleUnit]
LA.clockPeriod=20

# User data signals
LA.totalSignals=8
# Big endian (1) or Little endian (0).
LA.signalGroups=7
# Group 0
LA.groupName.0=MISO
LA.groupSize.0=1
LA.groupEndian.0=0
# Group 1
LA.groupName.1=MOSI
LA.groupSize.1=1
LA.groupEndian.1=0
# Group 2
LA.groupName.2=SSEL
LA.groupSize.2=1
LA.groupEndian.2=0
# Group 3
LA.groupName.3=SCK
LA.groupSize.3=1
LA.groupEndian.3=0
# Group 4
LA.groupName.4=interrupt_ack
LA.groupSize.4=1
LA.groupEndian.4=0
# Group 5
LA.groupName.5=spi_output_valid_sing
LA.groupSize.5=1
LA.groupEndian.5=0
# Group 6
LA.groupName.6=cnt
LA.groupSize.6=2
LA.groupEndian.6=0
# Group 7
#LA.groupName.7=byte_data_send
#LA.groupSize.7=8
#LA.groupEndian.7=0
# Group 8
#LA.groupName.8=spi_to_send_7_0
#LA.groupSize.8=8
#LA.groupEndian.8=0