Subversion Repositories or1200_hp

--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm2_top/ise_or1200_cm2_top/ise_or1200_cm2_top.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm2_top.twx
or1200_top_cm2_top.ncd -o or1200_top_cm2_top.twr or1200_top_cm2_top.pcf -ucf
or1200_top_cm2_top.ucf

Design file:              or1200_top_cm2_top.ncd
Physical constraint file: or1200_top_cm2_top.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;

 352299 paths analyzed, 11138 endpoints analyzed, 59 failing endpoints
 59 timing errors detected. (59 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.505ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.385ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7 (FF)
  Destination:          or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
  Requirement:          7.120ns
  Data Path Delay:      7.327ns (Levels of Logic = 7)
  Clock Path Skew:      -0.143ns (1.120 - 1.263)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y45.AQ      Tcko                  0.450   or1200_top_cm2i/or1200_dc_top/spr_write_cml_1
                                                       or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7
    SLICE_X25Y46.C3      net (fanout=27)       0.614   or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1<7>
    SLICE_X25Y46.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_cs_cml_1<0>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/eear_sel111
    SLICE_X26Y44.A5      net (fanout=18)       0.590   or1200_top_cm2i/or1200_cpu/or1200_sprs/N105
    SLICE_X26Y44.A       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_sprs/sr_cml_1<6>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/eear_sel21
    SLICE_X27Y30.C6      net (fanout=30)       1.073   or1200_top_cm2i/or1200_cpu/or1200_sprs/N109
    SLICE_X27Y30.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_except/id_pc_cml_1<7>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>261
    SLICE_X26Y43.A5      net (fanout=1)        1.099   or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>261
    SLICE_X26Y43.A       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
    SLICE_X26Y43.B6      net (fanout=1)        0.154   N1474
    SLICE_X26Y43.B       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
    SLICE_X26Y46.C6      net (fanout=2)        0.444   or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
    SLICE_X26Y46.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
                                                       or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
    SLICE_X28Y46.A6      net (fanout=4)        0.886   or1200_top_cm2i/rf_dataw<6>
    SLICE_X28Y46.A       Tilo                  0.094   pm_dc_gate_o_OBUF
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
    SLICE_X28Y44.BX      net (fanout=2)        0.439   or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
    SLICE_X28Y44.CLK     Tds                   0.920   or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    -------------------------------------------------  ---------------------------
    Total                                      7.327ns (2.028ns logic, 5.299ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.339ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4 (FF)
  Destination:          or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
  Requirement:          7.120ns
  Data Path Delay:      7.263ns (Levels of Logic = 7)
  Clock Path Skew:      -0.161ns (1.120 - 1.281)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y45.BQ      Tcko                  0.450   or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4
    SLICE_X30Y47.D5      net (fanout=64)       0.957   or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<4>
    SLICE_X30Y47.D       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
                                                       or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
    SLICE_X30Y47.B2      net (fanout=1)        0.774   or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
    SLICE_X30Y47.B       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
                                                       or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux00002232
    SLICE_X27Y51.C5      net (fanout=12)       0.946   or1200_top_cm2i/or1200_cpu/or1200_cfgr/N2
    SLICE_X27Y51.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_rf/rf_addra_reg_cml_1<3>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
    SLICE_X26Y43.A6      net (fanout=1)        0.635   or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
    SLICE_X26Y43.A       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
    SLICE_X26Y43.B6      net (fanout=1)        0.154   N1474
    SLICE_X26Y43.B       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
    SLICE_X26Y46.C6      net (fanout=2)        0.444   or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
    SLICE_X26Y46.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
                                                       or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
    SLICE_X28Y46.A6      net (fanout=4)        0.886   or1200_top_cm2i/rf_dataw<6>
    SLICE_X28Y46.A       Tilo                  0.094   pm_dc_gate_o_OBUF
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
    SLICE_X28Y44.BX      net (fanout=2)        0.439   or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
    SLICE_X28Y44.CLK     Tds                   0.920   or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    -------------------------------------------------  ---------------------------
    Total                                      7.263ns (2.028ns logic, 5.235ns route)
                                                       (27.9% logic, 72.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.321ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5 (FF)
  Destination:          or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
  Requirement:          7.120ns
  Data Path Delay:      7.245ns (Levels of Logic = 7)
  Clock Path Skew:      -0.161ns (1.120 - 1.281)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y45.CQ      Tcko                  0.450   or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5
    SLICE_X30Y47.D6      net (fanout=25)       0.939   or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
    SLICE_X30Y47.D       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
                                                       or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
    SLICE_X30Y47.B2      net (fanout=1)        0.774   or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
    SLICE_X30Y47.B       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
                                                       or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux00002232
    SLICE_X27Y51.C5      net (fanout=12)       0.946   or1200_top_cm2i/or1200_cpu/or1200_cfgr/N2
    SLICE_X27Y51.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_rf/rf_addra_reg_cml_1<3>
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
    SLICE_X26Y43.A6      net (fanout=1)        0.635   or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
    SLICE_X26Y43.A       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
    SLICE_X26Y43.B6      net (fanout=1)        0.154   N1474
    SLICE_X26Y43.B       Tilo                  0.094   or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
                                                       or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
    SLICE_X26Y46.C6      net (fanout=2)        0.444   or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
    SLICE_X26Y46.C       Tilo                  0.094   or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
                                                       or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
    SLICE_X28Y46.A6      net (fanout=4)        0.886   or1200_top_cm2i/rf_dataw<6>
    SLICE_X28Y46.A       Tilo                  0.094   pm_dc_gate_o_OBUF
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
    SLICE_X28Y44.BX      net (fanout=2)        0.439   or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
    SLICE_X28Y44.CLK     Tds                   0.920   or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
                                                       or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
    -------------------------------------------------  ---------------------------
    Total                                      7.245ns (2.028ns logic, 5.217ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.313ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0 (FF)
  Destination:          or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.324ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.156 - 0.145)
  Source Clock:         clk_i_BUFGP rising at 7.120ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0 to or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y63.AQ      Tcko                  0.414   or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1<1>
                                                       or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0
    SLICE_X32Y63.BX      net (fanout=2)        0.152   or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1<0>
    SLICE_X32Y63.CLK     Tckdi       (-Th)     0.242   or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3<1>
                                                       or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0
    -------------------------------------------------  ---------------------------
    Total                                      0.324ns (0.172ns logic, 0.152ns route)
                                                       (53.1% logic, 46.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.318ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm2i/iwb_biu/wb_adr_o_30 (FF)
  Destination:          or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.356ns (Levels of Logic = 0)
  Clock Path Skew:      0.038ns (0.183 - 0.145)
  Source Clock:         clk_i_BUFGP rising at 7.120ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm2i/iwb_biu/wb_adr_o_30 to or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y55.DQ       Tcko                  0.414   or1200_top_cm2i/iwb_biu/wb_adr_o<30>
                                                       or1200_top_cm2i/iwb_biu/wb_adr_o_30
    SLICE_X2Y55.CX       net (fanout=2)        0.160   or1200_top_cm2i/iwb_biu/wb_adr_o<30>
    SLICE_X2Y55.CLK      Tckdi       (-Th)     0.218   or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1<31>
                                                       or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30
    -------------------------------------------------  ---------------------------
    Total                                      0.356ns (0.196ns logic, 0.160ns route)
                                                       (55.1% logic, 44.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.322ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26 (FF)
  Destination:          or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.359ns (Levels of Logic = 0)
  Clock Path Skew:      0.037ns (0.177 - 0.140)
  Source Clock:         clk_i_BUFGP rising at 7.120ns
  Destination Clock:    clk_i_BUFGP rising at 7.120ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26 to or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y45.DQ       Tcko                  0.414   or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r<26>
                                                       or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26
    SLICE_X2Y45.CX       net (fanout=2)        0.163   or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r<26>
    SLICE_X2Y45.CLK      Tckdi       (-Th)     0.218   or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1<27>
                                                       or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26
    -------------------------------------------------  ---------------------------
    Total                                      0.359ns (0.196ns logic, 0.163ns route)
                                                       (54.6% logic, 45.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
  Period: 7.120ns
  High pulse: 3.560ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o<0>/SR
  Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0/SR
  Location pin: OLOGIC_X0Y46.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
  Period: 7.120ns
  High pulse: 3.560ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_3/SR
  Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_3/SR
  Location pin: OLOGIC_X2Y42.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
  Period: 7.120ns
  High pulse: 3.560ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_2/SR
  Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_2/SR
  Location pin: OLOGIC_X2Y41.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i          |    7.505|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 59  Score: 5950  (Setup/Max: 5950, Hold: 0)

Constraints cover 352299 paths, 0 nets, and 24617 connections

Design statistics:
   Minimum period:   7.505ns{1}   (Maximum frequency: 133.245MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Oct 21 15:15:09 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 317 MB