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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3_top/] [or1200_top_cm3_top.twr] - Rev 2

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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm3_top/ise_or1200_cm3_top/ise_or1200_cm3_top.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm3_top.twx
or1200_top_cm3_top.ncd -o or1200_top_cm3_top.twr or1200_top_cm3_top.pcf -ucf
or1200_top_cm3_top.ucf

Design file:              or1200_top_cm3_top.ncd
Physical constraint file: or1200_top_cm3_top.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;

 115046 paths analyzed, 14528 endpoints analyzed, 715 failing endpoints
 715 timing errors detected. (715 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.818ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.938ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.398ns (Levels of Logic = 3)
  Clock Path Skew:      -0.385ns (1.135 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL3 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A4      net (fanout=1)        1.045   or1200_top_cm3i/or1200_ic_top/tag<2>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X31Y76.C5      net (fanout=3)        1.287   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X31Y76.CLK     Tas                   0.029   or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2
                                                       or1200_top_cm3i/or1200_ic_top/icqmem_ack_o
                                                       or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.398ns (3.066ns logic, 2.332ns route)
                                                       (56.8% logic, 43.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.884ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.343ns (Levels of Logic = 3)
  Clock Path Skew:      -0.386ns (1.134 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL3 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A4      net (fanout=1)        1.045   or1200_top_cm3i/or1200_ic_top/tag<2>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X32Y75.B6      net (fanout=3)        1.258   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X32Y75.CLK     Tas                   0.003   or1200_top_cm3i/or1200_ic_top/or1200_ic_fsm/biudata_error_cml_2
                                                       or1200_top_cm3i/or1200_immu_top/icpu_rty_o1
                                                       or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.343ns (3.040ns logic, 2.303ns route)
                                                       (56.9% logic, 43.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.776ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.236ns (Levels of Logic = 3)
  Clock Path Skew:      -0.385ns (1.135 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL2 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A5      net (fanout=1)        0.883   or1200_top_cm3i/or1200_ic_top/tag<1>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X31Y76.C5      net (fanout=3)        1.287   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X31Y76.CLK     Tas                   0.029   or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2
                                                       or1200_top_cm3i/or1200_ic_top/icqmem_ack_o
                                                       or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.236ns (3.066ns logic, 2.170ns route)
                                                       (58.6% logic, 41.4% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.342ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.353ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.159 - 0.148)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y82.BQ      Tcko                  0.433   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25
    SLICE_X41Y82.AX      net (fanout=1)        0.149   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<25>
    SLICE_X41Y82.CLK     Tckdi       (-Th)     0.229   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25
    -------------------------------------------------  ---------------------------
    Total                                      0.353ns (0.204ns logic, 0.149ns route)
                                                       (57.8% logic, 42.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.349ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.474ns (Levels of Logic = 0)
  Clock Path Skew:      0.125ns (1.277 - 1.152)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y79.BQ      Tcko                  0.414   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<23>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21
    SLICE_X41Y81.AX      net (fanout=1)        0.289   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<21>
    SLICE_X41Y81.CLK     Tckdi       (-Th)     0.229   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<24>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21
    -------------------------------------------------  ---------------------------
    Total                                      0.474ns (0.185ns logic, 0.289ns route)
                                                       (39.0% logic, 61.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.351ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.362ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.159 - 0.148)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y82.DQ      Tcko                  0.433   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27
    SLICE_X41Y82.CX      net (fanout=1)        0.147   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
    SLICE_X41Y82.CLK     Tckdi       (-Th)     0.218   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27
    -------------------------------------------------  ---------------------------
    Total                                      0.362ns (0.215ns logic, 0.147ns route)
                                                       (59.4% logic, 40.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o<0>/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0/SR
  Location pin: OLOGIC_X2Y54.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR
  Location pin: OLOGIC_X0Y43.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR
  Location pin: OLOGIC_X2Y64.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i          |    5.818|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 715  Score: 177497  (Setup/Max: 177497, Hold: 0)

Constraints cover 115046 paths, 0 nets, and 27301 connections

Design statistics:
   Minimum period:   5.818ns{1}   (Maximum frequency: 171.880MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Oct 21 15:44:55 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 336 MB
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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3_top/] [or1200_top_cm3_top.twr] - Rev 2
