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[/] [p9813_rgb_led_string_driver/] [trunk/] [rtl/] [VHDL/] [function_pack.vhd] - Rev 2
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-- A package containing various conversion functions -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use std.textio.all; package function_pack is ------------------------------------------------------------------------------------ -- function calls ------------------------------------------------------------------------------------ function char2u(in_char : character) return unsigned; function str2u(in_string : string; out_size:integer) return unsigned; function asciichar2u2(d:character) return unsigned; -- Loosely based on code in Thesis by Rudi Rughoonundon, 11-1-1996 function str2u(s: string) return unsigned; function u_reverse(in_vect : unsigned) return unsigned; function u_recursive_parity ( x : unsigned ) return std_logic; function bit_width (maxval : integer) return integer; function bit_width (maxval : real) return integer; function timer_width (maxval : integer) return integer; function timer_width (maxval : real) return integer; end function_pack; package body function_pack is ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function char2u(in_char : character) return unsigned is variable out_vec : unsigned(3 downto 0); begin case in_char is when '0' => out_vec := "0000"; when '1' => out_vec := "0001"; when '2' => out_vec := "0010"; when '3' => out_vec := "0011"; when '4' => out_vec := "0100"; when '5' => out_vec := "0101"; when '6' => out_vec := "0110"; when '7' => out_vec := "0111"; when '8' => out_vec := "1000"; when '9' => out_vec := "1001"; when 'A' | 'a' => out_vec := "1010"; when 'B' | 'b' => out_vec := "1011"; when 'C' | 'c' => out_vec := "1100"; when 'D' | 'd' => out_vec := "1101"; when 'E' | 'e' => out_vec := "1110"; when 'F' | 'f' => out_vec := "1111"; when others => out_vec := "0000"; end case; return out_vec; end char2u; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function str2u(in_string : string; out_size:integer) return unsigned is variable uval : unsigned(out_size-1 downto 0); variable nibble : unsigned(3 downto 0); begin uval := (others=>'0'); for j in in_string'range loop uval(uval'length-1 downto 4) := uval(uval'length-5 downto 0); uval(3 downto 0) := char2u(in_string(j)); end loop; return uval; end str2u; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function asciichar2u2(d:character) return unsigned is variable dout : unsigned(0 to 7); variable ascii_int : integer := 0; variable val : integer := 0; begin -- Get integer value of the character ascii_int := character'pos(d); for index in dout'range loop val := ascii_int rem 2; ascii_int := ascii_int/2; if val=0 then dout(dout'high-index):='0'; else dout(dout'high-index):='1'; end if; end loop; return dout; end asciichar2u2; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ -- converts a string into std_logic_vector function str2u(s: string) return unsigned is variable uv: unsigned(8*s'high-1 downto 0); variable k: integer; begin k := s'high-s'low; for i in s'range loop -- uv(8*k+7 downto 8*k) := unsigned(chartobyte(s(i))); uv(8*k+7 downto 8*k) := asciichar2u2(s(i)); k := k - 1; end loop; return uv; end str2u; ------------------------------------------------------------------------------------ -- Bit Reverses the input vector ------------------------------------------------------------------------------------ function u_reverse(in_vect : unsigned) return unsigned is variable i : integer; variable o_vect : unsigned(in_vect'length-1 downto 0); begin for i in in_vect'length-1 downto 0 loop o_vect(in_vect'length-1-i) := in_vect(i); end loop; return(o_vect); end u_reverse; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ --* Title : TEST_PARITY --* Filename & Ext : test_parity.vhdl --* Author : David Bishop X-66788 --* Created : 3/18/97 --* Version : 1.2 --* Revision Date : 97/04/15 --* SCCSid : 1.2 04/15/97 test_parity.vhdl --* WORK Library : testchip --* Mod History : --* Description : This is a parity generator which is written recursively --* : It is designed to test the ability of Simulation and --* : Synthesis tools to check this capability. --* Known Bugs : --* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * function u_recursive_parity ( x : unsigned ) return std_logic is variable Upper, Lower : std_logic; variable Half : integer; variable BUS_int : unsigned( x'length-1 downto 0 ); variable Result : std_logic; begin BUS_int := x; if ( BUS_int'length = 1 ) then Result := BUS_int ( BUS_int'left ); elsif ( BUS_int'length = 2 ) then Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left ); else Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right; Upper := u_recursive_parity ( BUS_int ( BUS_int'left downto Half )); Lower := u_recursive_parity ( BUS_int ( Half - 1 downto BUS_int'right )); Result := Upper xor Lower; end if; return Result; end; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function bit_width (maxval : integer) return integer is variable w : integer; begin if (maxval<2) then w := 1; else w := integer(ceil(log2(real(maxval)))); end if; return w; end bit_width; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function bit_width (maxval : real) return integer is variable w : integer; begin if (maxval<2.0) then w := 1; else w := integer(ceil(log2(maxval))); end if; return w; end bit_width; ------------------------------------------------------------------------------------ -- Timer width differs from bit width in the following way: -- Bit width gives a vector large enough to have maxval different states, but -- timer width gives a vector large enough to hold the quantity maxval. -- -- The difference is critical when using timers, since they often count down from -- the initial value, and trigger timeout at a value of 1... So for maxval equal -- to a power of two, an extra bit must be reserved. This is done by adding one -- to the maxval input... ------------------------------------------------------------------------------------ function timer_width (maxval : integer) return integer is variable w : integer; begin if (maxval<2) then w := 1; else w := integer(ceil(log2(real(maxval+1)))); end if; return w; end timer_width; ------------------------------------------------------------------------------------ -- ------------------------------------------------------------------------------------ function timer_width (maxval : real) return integer is variable w : integer; begin if (maxval<2.0) then w := 1; else w := integer(ceil(log2(maxval+1.0))); end if; return w; end timer_width; end function_pack;