Subversion Repositories pcie_ds_dma

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-------------------------------------------------------------------------------
-- Project    : Series-7 Integrated Block for PCI Express
-- File       : cl_a7pcie_x4_pcie_pipe_lane.vhd
-- Version    : 1.10
--
-- Description: PIPE per lane module for 7-Series PCIe Block
--
--
--
----------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity cl_a7pcie_x4_pcie_pipe_lane is
  generic
  (
    PIPE_PIPELINE_STAGES : integer := 0    -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
  );
  port
  (
    pipe_rx_char_is_k_o      :     out std_logic_vector( 1 downto 0);  -- Pipelined PIPE Rx Char Is K
    pipe_rx_data_o           :     out std_logic_vector(15 downto 0);  -- Pipelined PIPE Rx Data
    pipe_rx_valid_o          :     out std_logic;                      -- Pipelined PIPE Rx Data Valid
    pipe_rx_chanisaligned_o  :     out std_logic;                      -- Pipelined PIPE Rx Chan Is Aligned
    pipe_rx_status_o         :     out std_logic_vector( 2 downto 0);  -- Pipelined PIPE Rx Status
    pipe_rx_phy_status_o     :     out std_logic;                      -- Pipelined PIPE Rx Phy Status
    pipe_rx_elec_idle_o      :     out std_logic;                      -- Pipelined PIPE Rx Electrical Idle
    pipe_rx_polarity_i       :     in std_logic;                       -- PIPE Rx Polarity
    pipe_tx_compliance_i     :     in std_logic;                       -- PIPE Tx Compliance
    pipe_tx_char_is_k_i      :     in std_logic_vector( 1 downto 0);   -- PIPE Tx Char Is K
    pipe_tx_data_i           :     in std_logic_vector(15 downto 0);   -- PIPE Tx Data
    pipe_tx_elec_idle_i      :     in std_logic;                       -- PIPE Tx Electrical Idle
    pipe_tx_powerdown_i      :     in std_logic_vector( 1 downto 0);   -- PIPE Tx Powerdown
 
    pipe_rx_char_is_k_i      :     in std_logic_vector( 1 downto 0);   -- PIPE Rx Char Is K
    pipe_rx_data_i           :     in std_logic_vector(15 downto 0);   -- PIPE Rx Data
    pipe_rx_valid_i          :     in std_logic;                       -- PIPE Rx Data Valid
    pipe_rx_chanisaligned_i  :     in std_logic;                       -- PIPE Rx Chan Is Aligned
    pipe_rx_status_i         :     in std_logic_vector( 2 downto 0);   -- PIPE Rx Status
    pipe_rx_phy_status_i     :     in std_logic;                       -- PIPE Rx Phy Status
    pipe_rx_elec_idle_i      :     in std_logic;                       -- PIPE Rx Electrical Idle
    pipe_rx_polarity_o       :     out std_logic;                      -- Pipelined PIPE Rx Polarity
    pipe_tx_compliance_o     :     out std_logic;                      -- Pipelined PIPE Tx Compliance
    pipe_tx_char_is_k_o      :     out std_logic_vector( 1 downto 0);  -- Pipelined PIPE Tx Char Is K
    pipe_tx_data_o           :     out std_logic_vector(15 downto 0);  -- Pipelined PIPE Tx Data
    pipe_tx_elec_idle_o      :     out std_logic;                      -- Pipelined PIPE Tx Electrical
    pipe_tx_powerdown_o      :     out std_logic_vector( 1 downto 0);  -- Pipelined PIPE Tx Powerdown
 
    pipe_clk                 :     in std_logic;                       -- PIPE Clock
    rst_n                    :     in std_logic                        -- Reset
  );
end cl_a7pcie_x4_pcie_pipe_lane;
 
 
architecture rtl of cl_a7pcie_x4_pcie_pipe_lane is
 
  --******************************************************************--
  -- Reality check.                                                   --
  --******************************************************************--
  constant TCQ     : integer := 1;
  signal pipe_rx_char_is_k_q                      : std_logic_vector(1 downto 0);
  signal pipe_rx_data_q                           : std_logic_vector(15 downto 0);
  signal pipe_rx_valid_q                          : std_logic;
  signal pipe_rx_chanisaligned_q                  : std_logic;
  signal pipe_rx_status_q                         : std_logic_vector(2 downto 0);
  signal pipe_rx_phy_status_q                     : std_logic;
  signal pipe_rx_elec_idle_q                      : std_logic;
 
  signal pipe_rx_polarity_q                       : std_logic;
  signal pipe_tx_compliance_q                     : std_logic;
  signal pipe_tx_char_is_k_q                      : std_logic_vector(1 downto 0);
  signal pipe_tx_data_q                           : std_logic_vector(15 downto 0);
  signal pipe_tx_elec_idle_q                      : std_logic;
  signal pipe_tx_powerdown_q                      : std_logic_vector(1 downto 0);
 
  signal pipe_rx_char_is_k_qq                     : std_logic_vector(1 downto 0);
  signal pipe_rx_data_qq                          : std_logic_vector(15 downto 0);
  signal pipe_rx_valid_qq                         : std_logic;
  signal pipe_rx_chanisaligned_qq                 : std_logic;
  signal pipe_rx_status_qq                        : std_logic_vector(2 downto 0);
  signal pipe_rx_phy_status_qq                    : std_logic;
  signal pipe_rx_elec_idle_qq                     : std_logic;
 
  signal pipe_rx_polarity_qq                      : std_logic;
  signal pipe_tx_compliance_qq                    : std_logic;
  signal pipe_tx_char_is_k_qq                     : std_logic_vector(1 downto 0);
  signal pipe_tx_data_qq                          : std_logic_vector(15 downto 0);
  signal pipe_tx_elec_idle_qq                     : std_logic;
  signal pipe_tx_powerdown_qq                     : std_logic_vector(1 downto 0);
 
begin  -- rtl
 
  pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
 
    pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
    pipe_rx_data_o <= pipe_rx_data_i;
    pipe_rx_valid_o <= pipe_rx_valid_i;
    pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
    pipe_rx_status_o <= pipe_rx_status_i;
    pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
    pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
 
    pipe_rx_polarity_o <= pipe_rx_polarity_i;
    pipe_tx_compliance_o <= pipe_tx_compliance_i;
    pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
    pipe_tx_data_o <= pipe_tx_data_i;
    pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
    pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
 
  end generate;  -- pipe_stages_0
 
  pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
 
    process (pipe_clk)
    begin
      if (pipe_clk'event and pipe_clk = '1') then
 
        if (rst_n = '1') then
 
          pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
          pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
          pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
          pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
          pipe_rx_status_q <= "000" after (TCQ)*1 ps;
          pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
          pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
          pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
          pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
          pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
          pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
          pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
 
        else
 
          pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
          pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
          pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
          pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
          pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
          pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
          pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
          pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
          pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
          pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
          pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
          pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
 
        end if;
      end if;
    end process;
 
    pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
    pipe_rx_data_o <= pipe_rx_data_q;
    pipe_rx_valid_o <= pipe_rx_valid_q;
    pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
    pipe_rx_status_o <= pipe_rx_status_q;
    pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
    pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
 
    pipe_rx_polarity_o <= pipe_rx_polarity_q;
    pipe_tx_compliance_o <= pipe_tx_compliance_q;
    pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
    pipe_tx_data_o <= pipe_tx_data_q;
    pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
    pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
 
  end generate;                         -- pipe_stages_1
 
  pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
 
    process (pipe_clk)
    begin
      if (pipe_clk'event and pipe_clk = '1') then
 
        if (rst_n = '1') then
 
          pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
          pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
          pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
          pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
          pipe_rx_status_q <= "000" after (TCQ)*1 ps;
          pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
          pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
          pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
          pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
          pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
          pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
          pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
 
          pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
          pipe_rx_data_qq <= (others => '0') after (TCQ)*1 ps;
          pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
          pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
          pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
          pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
          pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
          pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
          pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
          pipe_tx_data_qq <= (others => '0') after (TCQ)*1 ps;
          pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
          pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
        else
 
          pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
          pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
          pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
          pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
          pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
          pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
          pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
          pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
          pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
          pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
          pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
          pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
 
          pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
          pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
          pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
          pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
          pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
          pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
 
          pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
          pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
          pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
          pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
          pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
          pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
          pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
        end if;
      end if;
    end process;
 
    pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
    pipe_rx_data_o <= pipe_rx_data_qq;
    pipe_rx_valid_o <= pipe_rx_valid_qq;
    pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
    pipe_rx_status_o <= pipe_rx_status_qq;
    pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
    pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
 
    pipe_rx_polarity_o <= pipe_rx_polarity_qq;
    pipe_tx_compliance_o <= pipe_tx_compliance_qq;
    pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
    pipe_tx_data_o <= pipe_tx_data_qq;
    pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
    pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
 
  end generate;                         -- pipe_stages_2
 
end rtl;