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Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [inout_logic_cw_import.log] - Rev 11
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INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCIExpress/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/inout_logic_cw.vhd" into library workINFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.