Subversion Repositories pcie_sg_dma

Release 12.3 - xst M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> 
Reading constraint file user_logic_cw.xcf.
XCF parsing done.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "xst_user_logic.prj"
Input Format                       : mixed
Synthesis Constraint File          : user_logic_cw.xcf

---- Target Parameters
Output File Name                   : "user_logic_cw.ngc"
Output Format                      : NGC
Target Device                      : xc6vlx240t-3ff784

---- Source Options
Entity Name                        : user_logic_cw
Top Module Name                    : user_logic_cw
Automatic Register Balancing       : no

---- Target Options
Add IO Buffers                     : NO
Pack IO Registers into IOBs        : Auto

---- General Options
Keep Hierarchy                     : NO
Bus Delimiter                      : ()
Hierarchy Separator                : /
Write Timing Constraints           : yes

---- Other Options
report_timing_constraint_problems  : warning

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Goal                  : SPEED

=========================================================================

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" into library work
Parsing entity <cntr_11_0_1a411d6ef586e892>.
Parsing architecture <cntr_11_0_1a411d6ef586e892_a> of entity <cntr_11_0_1a411d6ef586e892>.
Parsing package <conv_pkg>.
Parsing package body <conv_pkg>.
Parsing entity <srl17e>.
Parsing architecture <structural> of entity <srl17e>.
Parsing entity <synth_reg>.
Parsing architecture <structural> of entity <synth_reg>.
Parsing entity <synth_reg_reg>.
Parsing architecture <behav> of entity <synth_reg_reg>.
Parsing entity <single_reg_w_init>.
Parsing architecture <structural> of entity <single_reg_w_init>.
Parsing entity <synth_reg_w_init>.
Parsing architecture <structural> of entity <synth_reg_w_init>.
Parsing entity <convert_func_call>.
Parsing architecture <behavior> of entity <convert_func_call>.
Parsing entity <xlconvert>.
Parsing architecture <behavior> of entity <xlconvert>.
Parsing entity <constant_963ed6358a>.
Parsing architecture <behavior> of entity <constant_963ed6358a>.
Parsing entity <xlregister>.
Parsing architecture <behavior> of entity <xlregister>.
Parsing entity <constant_6293007044>.
Parsing architecture <behavior> of entity <constant_6293007044>.
Parsing entity <constant_19562ab42f>.
Parsing architecture <behavior> of entity <constant_19562ab42f>.
Parsing entity <xlcounter_free>.
Parsing architecture <behavior> of entity <xlcounter_free>.
Parsing entity <inverter_e5b38cca3b>.
Parsing architecture <behavior> of entity <inverter_e5b38cca3b>.
Parsing entity <logical_80f90b97d0>.
Parsing architecture <behavior> of entity <logical_80f90b97d0>.
Parsing entity <user_logic>.
Parsing architecture <structural> of entity <user_logic>.
Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" into library work
Parsing entity <xlclockdriver>.
Parsing architecture <behavior> of entity <xlclockdriver>.
Parsing entity <default_clock_driver>.
Parsing architecture <structural> of entity <default_clock_driver>.
Parsing entity <user_logic_cw>.
Parsing architecture <structural> of entity <user_logic_cw>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <user_logic_cw> (architecture <structural>) from library <work>.
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 814: Assignment to from_register15_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 815: Assignment to from_register16_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 818: Assignment to from_register19_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 819: Assignment to from_register1_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 830: Assignment to from_register2_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 842: Assignment to from_register_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 844: Assignment to to_register10_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 845: Assignment to to_register11_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 846: Assignment to to_register12_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 847: Assignment to to_register13_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 848: Assignment to to_register14_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 849: Assignment to to_register15_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 850: Assignment to to_register16_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 851: Assignment to to_register17_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 852: Assignment to to_register18_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 853: Assignment to to_register19_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 854: Assignment to to_register1_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 855: Assignment to to_register20_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 856: Assignment to to_register21_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 857: Assignment to to_register22_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 858: Assignment to to_register23_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 859: Assignment to to_register24_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 860: Assignment to to_register25_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 861: Assignment to to_register26_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 862: Assignment to to_register27_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 863: Assignment to to_register2_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 864: Assignment to to_register3_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 865: Assignment to to_register4_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 866: Assignment to to_register5_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 867: Assignment to to_register6_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 868: Assignment to to_register7_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 869: Assignment to to_register8_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 870: Assignment to to_register9_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 871: Assignment to to_register_dout_net ignored, since the identifier is never used

Elaborating entity <default_clock_driver> (architecture <structural>) from library <work>.

Elaborating entity <xlclockdriver> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.
WARNING:HDLCompiler:89 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1751: <fdre> remains a black-box since it has no binding entity.

Elaborating entity <user_logic> (architecture <structural>) from library <work>.
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2634: Assignment to fifo_rd_count_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2637: Assignment to fifo_rd_pempty_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2639: Assignment to fifo_wr_count_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2640: Assignment to fifo_wr_full_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2641: Assignment to fifo_wr_pfull_net ignored, since the identifier is never used

Elaborating entity <constant_963ed6358a> (architecture <behavior>) from library <work>.

Elaborating entity <constant_6293007044> (architecture <behavior>) from library <work>.

Elaborating entity <constant_19562ab42f> (architecture <behavior>) from library <work>.

Elaborating entity <xlconvert> (architecture <behavior>) with generics from library <work>.

Elaborating entity <xlcounter_free> (architecture <behavior>) with generics from library <work>.

Elaborating entity <cntr_11_0_1a411d6ef586e892> (architecture <>) from library <work>.

Elaborating entity <inverter_e5b38cca3b> (architecture <behavior>) from library <work>.
WARNING:HDLCompiler:871 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2278: Using initial value false for op_mem_22_20_front_din since it is never assigned
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2284: Assignment to op_mem_22_20_back ignored, since the identifier is never used

Elaborating entity <logical_80f90b97d0> (architecture <behavior>) from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.
WARNING:HDLCompiler:89 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1762: <fdse> remains a black-box since it has no binding entity.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <user_logic_cw>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
    Set property "syn_black_box = true" for instance <persistentdff_inst>.
    Set property "syn_noprune = true" for instance <persistentdff_inst>.
    Set property "optimize_primitives = false" for instance <persistentdff_inst>.
    Set property "dont_touch = true" for instance <persistentdff_inst>.
    Set property "MAX_FANOUT = REDUCE" for signal <ce_1_sg_x0>.
    Set property "syn_keep = true" for signal <persistentdff_inst_q>.
    Set property "KEEP = TRUE" for signal <persistentdff_inst_q>.
WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <from_register15_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register16_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register19_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register1_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register2_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register10_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register11_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register12_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register13_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register14_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register15_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register16_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register17_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register18_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register19_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register1_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register20_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register21_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register22_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register23_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register24_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register25_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register26_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register27_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register2_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register3_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register4_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register5_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register6_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register7_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register8_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register9_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <user_logic_cw> synthesized.

Synthesizing Unit <default_clock_driver>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
    Set property "syn_noprune = true".
    Set property "optimize_primitives = false".
    Set property "dont_touch = true".
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <clr> of the instance <xlclockdriver> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <ce_logic> of the instance <xlclockdriver> is unconnected or connected to loadless signal.
    Summary:
        no macro.
Unit <default_clock_driver> synthesized.

Synthesizing Unit <xlclockdriver>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
        period = 1
        log_2_period = 1
        pipeline_regs = 5
        use_bufg = 0
    Set property "MAX_FANOUT = REDUCE" for signal <ce_vec>.
    Set property "MAX_FANOUT = REDUCE" for signal <ce_vec_logic>.
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 254: Output port <o> of the instance <clr_reg> is unconnected or connected to loadless signal.
    Summary:
        no macro.
Unit <xlclockdriver> synthesized.

Synthesizing Unit <synth_reg_w_init_1>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 0
        init_value = "0000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_1> synthesized.

Synthesizing Unit <single_reg_w_init_1>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 0
        init_value = "0000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_1> synthesized.

Synthesizing Unit <user_logic>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <fifo_rd_count<14:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <fifo_wr_count<14:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <fifo_rd_pempty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <fifo_wr_full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <fifo_wr_pfull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <user_logic> synthesized.

Synthesizing Unit <constant_963ed6358a>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_963ed6358a> synthesized.

Synthesizing Unit <constant_6293007044>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_6293007044> synthesized.

Synthesizing Unit <constant_19562ab42f>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_19562ab42f> synthesized.

Synthesizing Unit <xlconvert>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        din_width = 1
        din_bin_pt = 0
        din_arith = 1
        dout_width = 1
        dout_bin_pt = 0
        dout_arith = 1
        en_width = 1
        en_bin_pt = 0
        en_arith = 1
        bool_conversion = 1
        latency = 0
        quantization = 1
        overflow = 1
WARNING:Xst:647 - Input <en<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <xlconvert> synthesized.

Synthesizing Unit <xlcounter_free>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        core_name0 = "cntr_11_0_1a411d6ef586e892"
        op_width = 12
        op_arith = 1
    Set property "syn_black_box = true" for instance <comp0.core_instance0>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <up<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <load<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <din<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <xlcounter_free> synthesized.

Synthesizing Unit <inverter_e5b38cca3b>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <inverter_e5b38cca3b> synthesized.

Synthesizing Unit <logical_80f90b97d0>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <logical_80f90b97d0> synthesized.

Synthesizing Unit <xlregister_1>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 1
        init_value = "0"
    Summary:
        no macro.
Unit <xlregister_1> synthesized.

Synthesizing Unit <synth_reg_w_init_2>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 2
        init_value = "0"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_2> synthesized.

Synthesizing Unit <single_reg_w_init_2>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 2
        init_value = "0"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_2> synthesized.

Synthesizing Unit <xlregister_2>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_2> synthesized.

Synthesizing Unit <synth_reg_w_init_3>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_3> synthesized.

Synthesizing Unit <single_reg_w_init_3>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_3> synthesized.

Synthesizing Unit <xlregister_3>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000110000110100100011"
    Summary:
        no macro.
Unit <xlregister_3> synthesized.

Synthesizing Unit <synth_reg_w_init_4>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000110000110100100011"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_4> synthesized.

Synthesizing Unit <single_reg_w_init_4>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000110000110100100011"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_4> synthesized.

Synthesizing Unit <xlregister_4>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000100101011000000"
    Summary:
        no macro.
Unit <xlregister_4> synthesized.

Synthesizing Unit <synth_reg_w_init_5>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000100101011000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_5> synthesized.

Synthesizing Unit <single_reg_w_init_5>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000100101011000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_5> synthesized.

Synthesizing Unit <xlregister_5>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 12
        init_value = "000000000000"
    Summary:
        no macro.
Unit <xlregister_5> synthesized.

Synthesizing Unit <synth_reg_w_init_6>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 12
        init_index = 2
        init_value = "000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_6> synthesized.

Synthesizing Unit <single_reg_w_init_6>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 12
        init_index = 2
        init_value = "000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_6> synthesized.

Synthesizing Unit <xlregister_6>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 8
        init_value = "00000000"
    Summary:
        no macro.
Unit <xlregister_6> synthesized.

Synthesizing Unit <synth_reg_w_init_7>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 8
        init_index = 2
        init_value = "00000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_7> synthesized.

Synthesizing Unit <single_reg_w_init_7>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 8
        init_index = 2
        init_value = "00000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_7> synthesized.

Synthesizing Unit <xlregister_7>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 64
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_7> synthesized.

Synthesizing Unit <synth_reg_w_init_8>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 64
        init_index = 2
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_8> synthesized.

Synthesizing Unit <single_reg_w_init_8>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 64
        init_index = 2
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[32].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[33].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[34].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[35].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[36].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[37].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[38].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[39].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[40].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[41].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[42].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[43].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[44].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[45].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[46].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[47].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[48].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[49].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[50].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[51].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[52].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[53].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[54].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[55].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[56].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[57].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[58].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[59].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[60].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[61].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[62].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[63].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_8> synthesized.

Synthesizing Unit <xlregister_8>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 72
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_8> synthesized.

Synthesizing Unit <synth_reg_w_init_9>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 72
        init_index = 2
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_9> synthesized.

Synthesizing Unit <single_reg_w_init_9>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 72
        init_index = 2
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[32].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[33].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[34].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[35].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[36].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[37].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[38].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[39].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[40].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[41].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[42].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[43].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[44].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[45].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[46].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[47].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[48].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[49].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[50].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[51].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[52].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[53].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[54].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[55].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[56].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[57].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[58].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[59].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[60].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[61].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[62].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[63].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[64].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[65].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[66].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[67].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[68].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[69].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[70].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[71].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_9> synthesized.

Synthesizing Unit <xlregister_9>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000000000000000001"
    Summary:
        no macro.
Unit <xlregister_9> synthesized.

Synthesizing Unit <synth_reg_w_init_10>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000001"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_10> synthesized.

Synthesizing Unit <single_reg_w_init_10>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000001"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_10> synthesized.

Synthesizing Unit <xlregister_10>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "10000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_10> synthesized.

Synthesizing Unit <synth_reg_w_init_11>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "10000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_11> synthesized.

Synthesizing Unit <single_reg_w_init_11>.
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "10000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_11> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <xlpersistentdff.ngc>.
Reading core <cntr_11_0_1a411d6ef586e892.ngc>.
Loading core <xlpersistentdff> for timing and area information for instance <persistentdff_inst>.
Loading core <cntr_11_0_1a411d6ef586e892> for timing and area information for instance <comp0.core_instance0>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1145
 Flip-Flops                                            : 1145

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant10> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant11> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant12> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant19> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant20> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant21> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant22> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant23> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant24> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant25> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant26> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant3> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant4> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant7> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant8> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant9> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant14>, <constant15> of unit <constant_6293007044> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant14>, <constant6> of unit <constant_6293007044> are equivalent, second instance is removed

Optimizing unit <user_logic_cw> ...

Optimizing unit <user_logic> ...

Optimizing unit <single_reg_w_init_8> ...

Optimizing unit <single_reg_w_init_3> ...

Optimizing unit <single_reg_w_init_9> ...

Optimizing unit <single_reg_w_init_4> ...

Optimizing unit <single_reg_w_init_5> ...

Optimizing unit <single_reg_w_init_6> ...

Optimizing unit <single_reg_w_init_7> ...

Optimizing unit <single_reg_w_init_10> ...

Optimizing unit <single_reg_w_init_11> ...

Mapping all equations...
Annotating constraints using XCF file 'user_logic_cw.xcf'
XCF parsing done.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block user_logic_cw, actual ratio is 0.
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 2 FFs/Latches : <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 7 FFs/Latches : <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1145
 Flip-Flops                                            : 1145

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : user_logic_cw.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 40
#      GND                         : 2
#      INV                         : 3
#      LUT1                        : 10
#      MUXCY                       : 11
#      VCC                         : 2
#      XORCY                       : 12
# FlipFlops/Latches                : 1158
#      FD                          : 1
#      FDRE                        : 1142
#      FDSE                        : 15
# Others                           : 1
#      TIMESPEC                    : 1

Device utilization summary:
---------------------------

Selected Device : 6vlx240tff784-3 


Slice Logic Utilization: 
 Number of Slice Registers:            1158  out of  301440     0%  
 Number of Slice LUTs:                   13  out of  150720     0%  
    Number used as Logic:                13  out of  150720     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   1158
   Number with an unused Flip Flop:       0  out of   1158     0%  
   Number with an unused LUT:          1145  out of   1158    98%  
   Number of fully used LUT-FF pairs:    13  out of   1158     1%  
   Number of unique control sets:        17

IO Utilization: 
 Number of IOs:                        1976
 Number of bonded IOBs:                   0  out of    400     0%  

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                                                                      | Load  |
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
to_register_clk                    | NONE(default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp)| 1158  |
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 1.188ns (Maximum Frequency: 841.680MHz)
   Minimum input arrival time before clock: 0.349ns
   Maximum output required time after clock: 0.280ns
   Maximum combinational path delay: 0.000ns

=========================================================================
Timing constraint: TS_clk_5cc36873 = PERIOD TIMEGRP "clk_5cc36873" 5 nS HIGH 2.500 nS
  Clock period: 1.188ns (frequency: 841.680MHz)
  Total number of paths / destination ports: 1059 / 993
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  3.812ns
  Source:               user_logic_x0/counter4/comp0.core_instance0/BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_1 (FF)
  Destination:          user_logic_x0/counter4/comp0.core_instance0/BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_12 (FF)
  Data Path Delay:      1.188ns (Levels of Logic = 13)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 5.000ns

  Data Path: user_logic_x0/counter4/comp0.core_instance0/BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_1 (FF) to user_logic_x0/counter4/comp0.core_instance0/BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_12 (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.280   0.289  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_1 (q(0))
     INV:I->O              1   0.070   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/Mxor_i_simple_model.halfsum_0_xo<0>1_INV_0 (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.halfsum(0))
     MUXCY:S->O            1   0.219   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.carrymux0 (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(0))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(1))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(2))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(3))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(4))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(5))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(6))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(7))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(8))
     MUXCY:CI->O           1   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(9))
     MUXCY:CI->O           0   0.015   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple(10))
     XORCY:CI->O           1   0.180   0.000  U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carryxortop (U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/sum_simple(11))
     FDRE:D                   -0.012          U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_12
    ----------------------------------------
    Total                      1.188ns (0.899ns logic, 0.289ns route)
                                       (75.7% logic, 24.3% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock to_register_clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
to_register_clk|    1.188|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 11.14 secs
 
--> 

Total memory usage is 169716 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  444 (   0 filtered)
Number of infos    :   18 (   0 filtered)