Subversion Repositories pcie_sg_dma

##############################################################
#
# Xilinx Core Generator version 12.3
# Date: Thu Mar 08 11:05:57 2012
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 5.3
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=v6_eb_fifo_counted_new
CSET data_count=false
CSET data_count_width=15
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4096
CSET empty_threshold_negate_value=4097
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=28671
CSET full_threshold_negate_value=28670
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=72
CSET input_depth=32768
CSET output_data_width=72
CSET output_depth=32768
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=15
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=true
CSET write_data_count_width=15
# END Parameters
GENERATE
# CRC: 535701e3