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Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE12.1/] [v6_eb_fifo_counted_new_readme.txt] - Rev 11
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The following files were generated for 'v6_eb_fifo_counted_new' in directory
C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_User\ipcore_dir\
fifo_generator_ug175.pdf:
Please see the core data sheet.
v6_eb_fifo_counted_new.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
v6_eb_fifo_counted_new.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
v6_eb_fifo_counted_new.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
v6_eb_fifo_counted_new.sym:
Please see the core data sheet.
v6_eb_fifo_counted_new.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
v6_eb_fifo_counted_new.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
v6_eb_fifo_counted_new.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
v6_eb_fifo_counted_new.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
v6_eb_fifo_counted_new.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
v6_eb_fifo_counted_new.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
v6_eb_fifo_counted_new_readme.txt:
Text file indicating the files generated and how they are used.
v6_eb_fifo_counted_new_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
v6_eb_fifo_counted_new_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.