URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [coregen.log] - Rev 11
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INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Block_Memory_Generator v3.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Block_Memory_Generator v3.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
Project, 'coregen', initialised from file 'C:\Temp\Xilinx PCI
Express\pcie-v6-ml605_ISE12_User\ipcore_dir\coregen.cgp'.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
selected IP Fifo_Generator v5.3 to a more recent version.
Customizing IP...
Release 12.3 - Xilinx CORE Generator IP GUI Launcher M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Cancelled Customization.