URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [tmp/] [_cg/] [_dbg/] [xil_706.in] - Rev 11
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SET_FLAG DEBUG FALSESET_FLAG MODE INTERACTIVESET_FLAG STANDALONE_MODE FALSESET_PREFERENCE devicefamily virtex6SET_PREFERENCE device xc6vlx240tSET_PREFERENCE speedgrade -1SET_PREFERENCE package ff1156SET_PREFERENCE verilogsim trueSET_PREFERENCE vhdlsim trueSET_PREFERENCE simulationfiles BehavioralSET_PREFERENCE busformat BusFormatAngleBracketNotRippedSET_PREFERENCE outputdirectory C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/SET_PREFERENCE workingdirectory C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/SET_PREFERENCE subworkingdirectory C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/_cg/SET_PREFERENCE transientdirectory C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/_cg/_dbg/SET_PREFERENCE designentry VHDLSET_PREFERENCE flowvendor Foundation_ISESET_PREFERENCE addpads falseSET_PREFERENCE projectname coregenSET_PREFERENCE formalverification falseSET_PREFERENCE asysymbol falseSET_PREFERENCE implementationfiletype NgcSET_PREFERENCE foundationsym falseSET_PREFERENCE createndf falseSET_PREFERENCE removerpms falseSET_PARAMETER Component_Name v6_bram4096x64SET_PARAMETER Interface_Type NativeSET_PARAMETER AXI_Type AXI4_FullSET_PARAMETER AXI_Slave_Type Memory_SlaveSET_PARAMETER Use_AXI_ID falseSET_PARAMETER AXI_ID_Width 4SET_PARAMETER Memory_Type True_Dual_Port_RAMSET_PARAMETER ecctype No_ECCSET_PARAMETER ECC falseSET_PARAMETER softecc falseSET_PARAMETER Use_Error_Injection_Pins falseSET_PARAMETER Error_Injection_Type Single_Bit_Error_InjectionSET_PARAMETER Use_Byte_Write_Enable trueSET_PARAMETER Byte_Size 8SET_PARAMETER Algorithm Minimum_AreaSET_PARAMETER Primitive 8kx2SET_PARAMETER Assume_Synchronous_Clk falseSET_PARAMETER Write_Width_A 64SET_PARAMETER Write_Depth_A 4096SET_PARAMETER Read_Width_A 64SET_PARAMETER Operating_Mode_A WRITE_FIRSTSET_PARAMETER Enable_A Always_EnabledSET_PARAMETER Write_Width_B 64SET_PARAMETER Read_Width_B 64SET_PARAMETER Operating_Mode_B WRITE_FIRSTSET_PARAMETER Enable_B Always_EnabledSET_PARAMETER Register_PortA_Output_of_Memory_Primitives falseSET_PARAMETER Register_PortA_Output_of_Memory_Core falseSET_PARAMETER Use_REGCEA_Pin falseSET_PARAMETER Register_PortB_Output_of_Memory_Primitives trueSET_PARAMETER Register_PortB_Output_of_Memory_Core falseSET_PARAMETER Use_REGCEB_Pin falseSET_PARAMETER register_porta_input_of_softecc falseSET_PARAMETER register_portb_output_of_softecc falseSET_PARAMETER Pipeline_Stages 0SET_PARAMETER Load_Init_File falseSET_PARAMETER Coe_File no_coe_file_loadedSET_PARAMETER Fill_Remaining_Memory_Locations falseSET_PARAMETER Remaining_Memory_Locations 0SET_PARAMETER Use_RSTA_Pin falseSET_PARAMETER Reset_Memory_Latch_A falseSET_PARAMETER Reset_Priority_A CESET_PARAMETER Output_Reset_Value_A 0SET_PARAMETER Use_RSTB_Pin falseSET_PARAMETER Reset_Memory_Latch_B falseSET_PARAMETER Reset_Priority_B CESET_PARAMETER Output_Reset_Value_B 0SET_PARAMETER Reset_Type SYNCSET_PARAMETER Additional_Inputs_for_Power_Estimation falseSET_PARAMETER Port_A_Clock 100SET_PARAMETER Port_A_Write_Rate 50SET_PARAMETER Port_B_Clock 100SET_PARAMETER Port_B_Write_Rate 50SET_PARAMETER Port_A_Enable_Rate 100SET_PARAMETER Port_B_Enable_Rate 100SET_PARAMETER Collision_Warnings ALLSET_PARAMETER Disable_Collision_Warnings falseSET_PARAMETER Disable_Out_of_Range_Warnings falseSET_SIM_PARAMETER c_family virtex6SET_SIM_PARAMETER c_xdevicefamily virtex6SET_SIM_PARAMETER c_elaboration_dir C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/_cg/SET_SIM_PARAMETER c_interface_type 0SET_SIM_PARAMETER c_axi_type 1SET_SIM_PARAMETER c_axi_slave_type 0SET_SIM_PARAMETER c_has_axi_id 0SET_SIM_PARAMETER c_axi_id_width 4SET_SIM_PARAMETER c_mem_type 2SET_SIM_PARAMETER c_byte_size 8SET_SIM_PARAMETER c_algorithm 1SET_SIM_PARAMETER c_prim_type 1SET_SIM_PARAMETER c_load_init_file 0SET_SIM_PARAMETER c_init_file_name no_coe_file_loadedSET_SIM_PARAMETER c_use_default_data 0SET_SIM_PARAMETER c_default_data 0SET_SIM_PARAMETER c_rst_type SYNCSET_SIM_PARAMETER c_has_rsta 0SET_SIM_PARAMETER c_rst_priority_a CESET_SIM_PARAMETER c_rstram_a 0SET_SIM_PARAMETER c_inita_val 0SET_SIM_PARAMETER c_has_ena 0SET_SIM_PARAMETER c_has_regcea 0SET_SIM_PARAMETER c_use_byte_wea 1SET_SIM_PARAMETER c_wea_width 8SET_SIM_PARAMETER c_write_mode_a WRITE_FIRSTSET_SIM_PARAMETER c_write_width_a 64SET_SIM_PARAMETER c_read_width_a 64SET_SIM_PARAMETER c_write_depth_a 4096SET_SIM_PARAMETER c_read_depth_a 4096SET_SIM_PARAMETER c_addra_width 12SET_SIM_PARAMETER c_has_rstb 0SET_SIM_PARAMETER c_rst_priority_b CESET_SIM_PARAMETER c_rstram_b 0SET_SIM_PARAMETER c_initb_val 0SET_SIM_PARAMETER c_has_enb 0SET_SIM_PARAMETER c_has_regceb 0SET_SIM_PARAMETER c_use_byte_web 1SET_SIM_PARAMETER c_web_width 8SET_SIM_PARAMETER c_write_mode_b WRITE_FIRSTSET_SIM_PARAMETER c_write_width_b 64SET_SIM_PARAMETER c_read_width_b 64SET_SIM_PARAMETER c_write_depth_b 4096SET_SIM_PARAMETER c_read_depth_b 4096SET_SIM_PARAMETER c_addrb_width 12SET_SIM_PARAMETER c_has_mem_output_regs_a 0SET_SIM_PARAMETER c_has_mem_output_regs_b 1SET_SIM_PARAMETER c_has_mux_output_regs_a 0SET_SIM_PARAMETER c_has_mux_output_regs_b 0SET_SIM_PARAMETER c_mux_pipeline_stages 0SET_SIM_PARAMETER c_has_softecc_input_regs_a 0SET_SIM_PARAMETER c_has_softecc_output_regs_b 0SET_SIM_PARAMETER c_use_softecc 0SET_SIM_PARAMETER c_use_ecc 0SET_SIM_PARAMETER c_has_injecterr 0SET_SIM_PARAMETER c_sim_collision_check ALLSET_SIM_PARAMETER c_common_clk 0SET_SIM_PARAMETER c_disable_warn_bhv_coll 0SET_SIM_PARAMETER c_disable_warn_bhv_range 0SET_CORE_NAME Block Memory GeneratorSET_CORE_VERSION 6.2SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2SET_CORE_PATH C:/Programmi/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2SET_CORE_GUIPATH C:/Programmi/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tclSET_CORE_DATASHEET C:\Programmi\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdfADD_CORE_DOCUMENT <C:\Programmi\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf>ADD_CORE_DOCUMENT <C:\Programmi\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html>