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https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_bram4096x64_fast_ste/] [implement/] [implement.sh] - Rev 13
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#!/bin/sh # Clean up the results directory rm -rf results mkdir results #Synthesize the Wrapper Files echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; echo 'Synthesizing example design with XST'; xst -ifn xst.scr cp v6_bram4096x64_fast_top.ngc ./results/ # Copy the netlist generated by Coregen echo 'Copying files from the netlist directory to the results directory' cp ../../v6_bram4096x64_fast.ngc results/ # Copy the constraints files generated by Coregen echo 'Copying files from constraints directory to results directory' cp ../example_design/v6_bram4096x64_fast_top.ucf results/ cd results echo 'Running ngdbuild' ngdbuild -p xc6vlx240t-ff1156-1 v6_bram4096x64_fast_top echo 'Running map' map v6_bram4096x64_fast_top -o mapped.ncd -pr i echo 'Running par' par mapped.ncd routed.ncd echo 'Running trce' trce -e 10 routed.ncd mapped.pcf -o routed echo 'Running design through bitgen' bitgen -w routed echo 'Running netgen to create gate level VHDL model' netgen -ofmt vhdl -sim -tm v6_bram4096x64_fast_top -pcf mapped.pcf -w routed.ncd routed.vhd