Subversion Repositories pcie_sg_dma

##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:17:44 2010
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=prim_FIFO_plain
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=5
CSET empty_threshold_negate_value=6
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Independent_Clocks_Builtin_FIFO
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=496
CSET full_threshold_negate_value=495
CSET input_data_width=72
CSET input_depth=512
CSET output_data_width=72
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=175
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=175
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: eccbbd21