Subversion Repositories plb2wbbridge

#!/usr/bin/ruby

# Usage: ruby fifo_generator [OPTIONS]... setup-file
#
#  OPTIONS:
#     
#     -c --no-coregen         do not run coregen (Only creates *.xco command_files)
#     -v --cp-vhdl-to-lib     copy vhdl-files to library folder 
#                             (path is set in 'setup-file')
#     -n --cp-ngc-to_imp      copy netlist-files to implementation folder 
#                             (path is set in 'setup_file')
#     -? --help               display this message
#
require 'pp'
require 'getoptlong'
require 'rdoc/usage'
#=======================================================================
# 
#    _____ _  __              ____                           _
#   |  ___(_)/ _| ___        / ___| ___ _ __   ___ _ __ __ _| |_ ___  _ __
#   | |_  | | |_ / _ \ _____| |  _ / _ \ '_ \ / _ \ '__/ _` | __/ _ \| '__|
#   |  _| | |  _| (_) |_____| |_| |  __/ | | |  __/ | | (_| | || (_) | |
#   |_|   |_|_|  \___/       \____|\___|_| |_|\___|_|  \__,_|\__\___/|_|
#   _______________________________________________
#                          _________________________________________________________
# 
# 
# 
#
#
#
#
#
#=======================================================================
#
#
#  Global constants/strings
#
#=======================================================================

BASE_INFO="
######################
#
#   Auto generated by 'fifo_generator.rb'.
#   Please modify only 'plb2wb_bridge.setup',
#   modifications to this file will be overwritten!
#
####
"
BASE_SELECT="
SELECT Fifo_Generator family Xilinx,_Inc. 5.3
"
# CSET use_extra_logic=false  ??
#=======================================================================
#
#
#  Global variables
#
#=======================================================================
$plb2wb_bridge_vhdl_dir    = nil
$plb2wb_bridge_ngc_dir     = nil
$address_buffer_size       = nil
$read_buffer_size          = nil
$write_buffer_size         = nil
$device                    = nil
$device_family             = nil
$package                   = nil
$speedgrade                = nil
$address_buffer_mindwidth  = nil
$read_buffer_dwidth        = nil
$write_buffer_dwidth       = nil
$wb_clk_frequency          = nil
$plb_clk_frequency         = nil
$mid2plb_buffer_size       = nil
$stat2plb_buffer_size      = nil
$stat2plb_buffer_mindwidth = nil
$stat2wb_buffer_size       = nil
$stat2wb_buffer_dwidth     = nil
$opt_no_coregen            = false
$opt_cp_vhdl               = false
$opt_cp_ngc                = false

#=======================================================================
#
#
# functions to set and check gloval variables
#
#=======================================================================
def all_items_set?

   all_items_set = true;

   if $address_buffer_size == nil 
      all_items_set = false;
      print "'Address_Buffer_Size' is not set in setup file\n"
   end
   if $read_buffer_size == nil 
      all_items_set = false;
      print "'Read_Buffer_Size' is not set in setup file\n"
   end
   if $write_buffer_size == nil 
      all_items_set = false;
      print "'Write_Buffer_Size' is not set in setup file\n"
   end
   if $device == nil
      all_items_set = false;
      print "'Device' is not set in setup file\n"
   end
   if $device_family  == nil
      all_items_set = false;
      print "'Device_Family' is not set in setup file\n"
   end
   if $package == nil
      all_items_set = false;
      print "'Package' is not set in setup file\n"
   end
   if $speedgrade == nil
      all_items_set = false;
      print "'Speedgrade' is not set in setup file\n"
   end
   if $address_buffer_mindwidth == nil
      all_items_set = false;
      print "'Address_Buffer_minDWidth' is not set in setup file\n"
   end
   if $read_buffer_dwidth == nil
      all_items_set = false;
      print "'Read_Buffer_DWidth' is not set in setup file\n"
   end
   if $write_buffer_dwidth == nil
      all_items_set = false;
      print "'Write_Buffer_DWidth' is not set in setup file\n"
   end
   if $wb_clk_frequency == nil
      all_items_set = false;
      print "'PLB_Clk_Frequency' is not set in setup file\n"
   end
   if $plb_clk_frequency == nil
      all_items_set = false;
      print "'WB_Clk_Frequency' is not set in setup file\n"
   end
   if $stat2plb_buffer_size == nil
      all_items_set = false;
      print "'Stat2PLB_Buffer_Size' is not set in setup file\n"
   end
   if $stat2plb_buffer_mindwidth == nil
      all_items_set = false;
      print "'Stat2PLB_Buffer_minDWidth' is not set in setup file\n"
   end
   if $stat2wb_buffer_size == nil
      all_items_set = false;
      print "'Stat2WB_Buffer_Size' is not set in setup file\n"
   end
   if $stat2wb_buffer_dwidth == nil
      all_items_set = false;
      print "'Stat2WB_Buffer_DWidth' is not set in setup file\n"
   end
   return all_items_set
end


def set_item( item, value )


   case item
      when "PLB2WB_Bridge_VHDL_DIR"
         $plb2wb_bridge_vhdl_dir = value
      when "Address_Buffer_Size"
         if value =~ /^[0-9]*$/
            $address_buffer_size = value
         else
            print "Invalid format for `Address_Buffer_Size` in setup file\n";exit
         end
      when "Read_Buffer_Size"
         if value =~ /^[0-9]*$/
            $read_buffer_size = value
         else
            print "Invalid format for `Read_Buffer_Size` in setup file\n";exit
         end
      when "Write_Buffer_Size"
         if value =~ /^[0-9]*$/
            $write_buffer_size = value
         else
            print "Invalid format for `Write_Buffer_Size` in setup file\n";exit
         end
      when "Device_Family"
         $device_family = value
      when "Device"
         $device = value
      when "Package"
         $package = value
      when "Speedgrade"
         if value =~ /^\-[0-9]*$/    
            $speedgrade = value
         end
      when "Address_Buffer_minDWidth"
         if value =~ /^[0-9]*$/
            $address_buffer_mindwidth = value
         else
            print "Invalid format for `Address_Buffer_minDWidth` in setup file\n";exit
         end
      when "Read_Buffer_DWidth"
         if value =~ /^[0-9]*$/
            $read_buffer_dwidth = value
         else
            print "Invalid format for `Read_Buffer_DWidth` in setup file\n";exit
         end
      when "Write_Buffer_DWidth"
         if value =~ /^[0-9]*$/
            $write_buffer_dwidth = value
         else
            print "Invalid format for `Write_Buffer_DWidth` in setup file\n";exit
         end
      when "WB_Clk_Frequency"
         if value =~ /^[0-9]*$/
            $wb_clk_frequency = value
         else
            print "Invalid format for `WB_Clk_Frequency` in setup file\n";exit
         end
      when "PLB_Clk_Frequency"
         if value =~ /^[0-9]*$/
            $plb_clk_frequency = value
         else
            print "Invalid format for `PLB_Clk_Frequency` in setup file\n";exit
         end
      when "PLB2WB_Bridge_NGC_DIR"
         $plb2wb_bridge_ngc_dir = value

      when "Stat2PLB_Buffer_Size"
         if value =~ /^[0-9]*$/
            $stat2plb_buffer_size = value
         else
            print "Invalid format for `Stat2PLB_Buffer_Size` in setup file\n";exit
         end

      when "Stat2PLB_Buffer_minDWidth"
         if value =~ /^[0-9]*$/
            $stat2plb_buffer_mindwidth = value
         else
            print "Invalid format for `Stat2PLB_Buffer_minDWidth` in setup file\n";exit
         end

      when "Stat2WB_Buffer_Size"
         if value =~ /^[0-9]*$/
            $stat2wb_buffer_size = value
         else
            print "Invalid format for `Stat2WB_Buffer_Size` in setup file\n";exit
         end

      when "Stat2WB_Buffer_DWidth"
         if value =~ /^[0-9]*$/
            $stat2wb_buffer_dwidth = value
         else
            print "Invalid format for `Stat2WB_Buffer_DWidth` in setup file\n";exit
         end

      end

end
#=======================================================================
#
#
# *.XCO-File generation helpers
#
#=======================================================================
def print_project_header( file )

   file.puts( "SET addpads = False"                   )
   file.puts( "SET asysymbol = True"                  )
   file.puts( "SET busformat = BusFormatParenNotRipped")
   file.puts( "SET createndf = False"                 )
   file.puts( "SET designentry = VHDL"                )
   file.puts( "SET device = "       + $device         )
   file.puts( "SET devicefamily = " + $device_family  )
   file.puts( "SET flowvendor = Other"                )
   file.puts( "SET formalverification = False"        )
   file.puts( "SET foundationsym = False"             )
   file.puts( "SET implementationfiletype = Ngc"      )
   file.puts( "SET package = "      + $package        )
   file.puts( "SET removerpms = False"                )
   file.puts( "SET simulationfiles = Structural"      )
   file.puts( "SET speedgrade = "   + $speedgrade     )
   file.puts( "SET verilogsim = False"                )
   file.puts( "SET vhdlsim = True"                    )
   



end


def print_fifo_parameters( file, independet_clocks, component_name, deepth, width, r_clk_frq, w_clk_frq, with_almost_empty )

   data_count_width = Math.log( deepth ) / Math.log( 2 )

   if with_almost_empty
      file.puts( "CSET almost_empty_flag=true"                 )
   else
      file.puts( "CSET almost_empty_flag=false"                )
   end
   file.puts( "CSET almost_full_flag=false"                    )
   file.puts( "CSET component_name=#{component_name}"          )
   file.puts( "CSET data_count=false"                          )
   file.puts( "CSET data_count_width=#{data_count_width.to_i}" )
   file.puts( "CSET disable_timing_violations=false"           )
   file.puts( "CSET dout_reset_value=0"                        )
   file.puts( "CSET empty_threshold_assert_value=1"            )
   file.puts( "CSET empty_threshold_negate_value=1"            )
   file.puts( "CSET enable_ecc=false"                          )
   file.puts( "CSET enable_int_clk=false"                      )
   file.puts( "CSET enable_reset_synchronization=true"         )
   if independet_clocks == false
   #common clocks
      if deepth.to_i < 512
         file.puts( "CSET fifo_implementation=Common_Clock_Distributed_RAM" )
      else
         if with_almost_empty
            file.puts( "CSET fifo_implementation=Common_Clock_Block_RAM" )
         else
            file.puts( "CSET fifo_implementation=Common_Clock_Builtin_FIFO" )
         end
      end
   else
   #independet clocks
      if deepth.to_i < 512
         file.puts( "CSET fifo_implementation=Independent_Clocks_Distributed_RAM" )
      else
         if with_almost_empty
            file.puts( "CSET fifo_implementation=Independent_Clocks_Block_RAM" )
         else
            file.puts( "CSET fifo_implementation=Independent_Clocks_Builtin_FIFO" )
         end
      end
   end
   file.puts( "CSET full_flags_reset_value=0"                  )
   file.puts( "CSET full_threshold_assert_value=1"             )
   file.puts( "CSET full_threshold_negate_value=1"             )
   file.puts( "CSET inject_dbit_error=false"                   )
   file.puts( "CSET inject_sbit_error=false"                   )
   file.puts( "CSET input_data_width=#{width}"                 )
   file.puts( "CSET input_depth=#{deepth}"                     )
   file.puts( "CSET output_data_width=#{width}"                )
   file.puts( "CSET output_depth=#{deepth}"                    )
   file.puts( "CSET overflow_flag=false"                       )
   file.puts( "CSET overflow_sense=Active_High"                )
   file.puts( "CSET performance_options=First_Word_Fall_Through"              )
   file.puts( "CSET programmable_empty_type=No_Programmable_Empty_Threshold"  )
   file.puts( "CSET programmable_full_type=No_Programmable_Full_Threshold"    )
   if deepth.to_i < 512 or independet_clocks == false
      file.puts( "CSET read_clock_frequency=1"               )
   else
      file.puts( "CSET read_clock_frequency=#{r_clk_frq}"               )
   end
   file.puts( "CSET read_data_count=false"                           )
   file.puts( "CSET read_data_count_width=#{data_count_width.to_i}"  )
   file.puts( "CSET reset_pin=true"                                  )
   file.puts( "CSET reset_type=Asynchronous_Reset"                   )
   file.puts( "CSET underflow_flag=false"                            )
   file.puts( "CSET underflow_sense=Active_High"                     )
   file.puts( "CSET use_dout_reset=false"                            )
   file.puts( "CSET use_embedded_registers=false"                    )
   file.puts( "CSET valid_flag=false"                                )
   file.puts( "CSET valid_sense=Active_High"                         )
   file.puts( "CSET write_acknowledge_flag=false"                    )
   file.puts( "CSET write_acknowledge_sense=Active_High"             )
   if deepth.to_i < 512 or independet_clocks == false
      file.puts( "CSET write_clock_frequency=1" )
   else
      file.puts( "CSET write_clock_frequency=#{w_clk_frq}" )
   end
   file.puts( "CSET write_data_count=false"                          )
   file.puts( "CSET write_data_count_width=#{data_count_width.to_i}" )


end
#======================================================================
#
#     XCO-File generation and syntehsis functions
#
#
#======================================================================



def generate_adr_fifos( independet_clocks )

   cc_or_ic = (independet_clocks == true)? "ic" : "cc"

   open( "fifo_adr_#{cc_or_ic}_1.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_adr_#{cc_or_ic}_1", 
                              $address_buffer_size, 
                              $address_buffer_mindwidth.to_i, 
                              $wb_clk_frequency, 
                              $plb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end



   open( "fifo_adr_#{cc_or_ic}_2.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_adr_#{cc_or_ic}_2",
                              $address_buffer_size, 
                              $address_buffer_mindwidth.to_i + 1, 
                              $wb_clk_frequency, 
                              $plb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end




   open( "fifo_adr_#{cc_or_ic}_3.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_adr_#{cc_or_ic}_3", 
                              $address_buffer_size, 
                              $address_buffer_mindwidth.to_i + 2, 
                              $wb_clk_frequency, 
                              $plb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end




   open( "fifo_adr_#{cc_or_ic}_4.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_adr_#{cc_or_ic}_4", 
                              $address_buffer_size, 
                              $address_buffer_mindwidth.to_i + 3, 
                              $wb_clk_frequency, 
                              $plb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end


   system( "coregen -b fifo_adr_#{cc_or_ic}_1.xco" ) if $opt_no_coregen == false 
   system( "coregen -b fifo_adr_#{cc_or_ic}_2.xco" ) if $opt_no_coregen == false 
   system( "coregen -b fifo_adr_#{cc_or_ic}_3.xco" ) if $opt_no_coregen == false 
   system( "coregen -b fifo_adr_#{cc_or_ic}_4.xco" ) if $opt_no_coregen == false 

end


def generate_wdat_fifos( independet_clocks )


   cc_or_ic = (independet_clocks == true)? "ic" : "cc"

   open( "fifo_wdat_#{cc_or_ic}_32.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_wdat_#{cc_or_ic}_32", 
                              $write_buffer_size, 
                              $write_buffer_dwidth.to_i, 
                              $wb_clk_frequency, 
                              $plb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end

   system( "coregen -b fifo_wdat_#{cc_or_ic}_32.xco" ) if $opt_no_coregen == false

end


def generate_rdat_fifos( independet_clocks )


   cc_or_ic = (independet_clocks == true)? "ic" : "cc"

   open( "fifo_rdat_#{cc_or_ic}_32.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_rdat_#{cc_or_ic}_32", 
                              $read_buffer_size, 
                              $read_buffer_dwidth.to_i, 
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              true )
      file.puts( "GENERATE" )
      file.close
   end

   system( "coregen -b fifo_rdat_#{cc_or_ic}_32.xco" ) if $opt_no_coregen == false

end


def  generate_stat2plb_fifos( independet_clocks  )

   cc_or_ic = (independet_clocks == true)? "ic" : "cc"
  


   open( "fifo_stat2plb_#{cc_or_ic}_1.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_stat2plb_#{cc_or_ic}_1", 
                              $stat2plb_buffer_size, 
                              $stat2plb_buffer_mindwidth.to_i, 
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end



   open( "fifo_stat2plb_#{cc_or_ic}_2.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_stat2plb_#{cc_or_ic}_2", 
                              $stat2plb_buffer_size, 
                              $stat2plb_buffer_mindwidth.to_i + 1, 
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end



   open( "fifo_stat2plb_#{cc_or_ic}_3.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_stat2plb_#{cc_or_ic}_3", 
                              $stat2plb_buffer_size, 
                              $stat2plb_buffer_mindwidth.to_i + 2, 
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end



   open( "fifo_stat2plb_#{cc_or_ic}_4.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_stat2plb_#{cc_or_ic}_4", 
                              $stat2plb_buffer_size, 
                              $stat2plb_buffer_mindwidth.to_i + 3, 
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end

   system( "coregen -b fifo_stat2plb_#{cc_or_ic}_1.xco" ) if $opt_no_coregen == false
   system( "coregen -b fifo_stat2plb_#{cc_or_ic}_2.xco" ) if $opt_no_coregen == false
   system( "coregen -b fifo_stat2plb_#{cc_or_ic}_3.xco" ) if $opt_no_coregen == false
   system( "coregen -b fifo_stat2plb_#{cc_or_ic}_4.xco" ) if $opt_no_coregen == false

end

def  generate_stat2wb_fifos( independet_clocks  )

   cc_or_ic = (independet_clocks == true)? "ic" : "cc"
   
   open( "fifo_stat2wb_#{cc_or_ic}.xco", "w" ) do |file|
      file.puts( BASE_INFO )
      print_project_header( file )
      file.puts( BASE_SELECT )
      print_fifo_parameters(  file, 
                              independet_clocks, 
                              "fifo_stat2wb_#{cc_or_ic}", 
                              $stat2wb_buffer_size, 
                              $stat2wb_buffer_dwidth.to_i,
                              $plb_clk_frequency, 
                              $wb_clk_frequency,
                              false )
      file.puts( "GENERATE" )
      file.close
   end

   system( "coregen -b fifo_stat2wb_#{cc_or_ic}.xco" ) if $opt_no_coregen == false

end



#=================================================================
#
#     Main-script starts here:
#
#=================================================================
opts= GetoptLong.new(
   ['--no-coregen',     '-c', GetoptLong::NO_ARGUMENT],
   ['--cp-vhdl-to-lib', '-v', GetoptLong::NO_ARGUMENT],
   ['--cp-ngc-to-imp',  '-n', GetoptLong::NO_ARGUMENT],
   ['--help',           '-?', GetoptLong::NO_ARGUMENT]
   )


opts.each do |opt, arg|
   case opt
      when '--no-coregen'
         $opt_no_coregen   = true
      when '--cp-vhdl-to-lib'
         $opt_cp_vhdl      = true
      when '--cp-ngc-to-imp'
         $opt_cp_ngc       = true
      when '--help'
         RDoc::usage
   end
end

if ARGV.length != 1
   RDoc::usage
end



if File.exists? ARGV[0]


   open( 'plb2wb_bridge.setup' ) do |file|
      file.each { |line| 

         # check, if this is a valid setup-line
         if line =~ /[\s]*([a-zA-Z0-9_]+)[\s]*=[\s]*([\-0-9a-zA-Z\.\/_]+)/
            set_item( $1, $2 )
         end
      }
   end
else
   print "#{ARGV[0]} not found!\n\n"
   RDoc::usage
end




if all_items_set?

   generate_stat2plb_fifos  ( true  )
   generate_stat2plb_fifos  ( false )
   generate_adr_fifos      ( true  )
   generate_adr_fifos      ( false )
   generate_wdat_fifos     ( true  )
   generate_wdat_fifos     ( false )
   generate_rdat_fifos     ( true  )
   generate_rdat_fifos     ( false )
   generate_stat2wb_fifos ( true  )
   generate_stat2wb_fifos ( false )



   if $opt_cp_vhdl
      if $plb2wb_bridge_vhdl_dir == nil 
         print "'PLB2WB_Bridge_VHDL_Dir' is not set in plb2wb_bridge.setup\n"
      else
         system( "cp *.vhd #{$plb2wb_bridge_vhdl_dir }" )
         print "Copy vhdl-files to '#{$plb2wb_bridge_vhdl_dir}'\n"
      end
   end

   if $opt_cp_ngc
      if $plb2wb_bridge_ngc_dir == nil 
         print "'PLB2WB_Bridge_NGC_Dir' is not set in plb2wb_bridge.setup\n"
      else
         print "Copy netlists to '#{$plb2wb_bridge_ngc_dir}'\n"
         system( "cp *.ngc #{$plb2wb_bridge_ngc_dir }" )
      end
   end

else
   print "Please complete 'plb2wb_bridge.setup'\n"
   exit
end




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