Subversion Repositories riscv_vhdl

/*
 *  Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
 *
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 */
 
#ifndef __DEBUGGER_RIVER_CFG_H__
#define __DEBUGGER_RIVER_CFG_H__
 
#include <systemc.h>
 
namespace debugger {
 
static const int RISCV_ARCH     = 64;
 
static const int BUS_ADDR_WIDTH = 32;
static const int BUS_DATA_WIDTH = 64;
static const int BUS_DATA_BYTES = BUS_DATA_WIDTH / 8;
 
static const uint8_t MEMOP_8B = 3;
static const uint8_t MEMOP_4B = 2;
static const uint8_t MEMOP_2B = 1;
static const uint8_t MEMOP_1B = 0;
 
static const uint64_t RESET_VECTOR      = 0x0040;
static const int DBG_FETCH_TRACE_SIZE   = 4;
 
/** Number of elements each 2*CFG_ADDR_WIDTH in stack trace buffer: */
static const int CFG_STACK_TRACE_BUF_SIZE = 32;
 
enum EIsaType {
    ISA_R_type,
    ISA_I_type,
    ISA_S_type,
    ISA_SB_type,
    ISA_U_type,
    ISA_UJ_type,
    ISA_Total
};
 
enum EInstuctionsType {
    Instr_ADD,
    Instr_ADDI,
    Instr_ADDIW,
    Instr_ADDW,
    Instr_AND,
    Instr_ANDI,
    Instr_AUIPC,
    Instr_BEQ,
    Instr_BGE,
    Instr_BGEU,
    Instr_BLT,
    Instr_BLTU,
    Instr_BNE,
    Instr_JAL,
    Instr_JALR,
    Instr_LB,
    Instr_LH,
    Instr_LW,
    Instr_LD,
    Instr_LBU,
    Instr_LHU,
    Instr_LWU,
    Instr_LUI,
    Instr_OR,
    Instr_ORI,
    Instr_SLLI,
    Instr_SLT,
    Instr_SLTI,
    Instr_SLTU,
    Instr_SLTIU,
    Instr_SLL,
    Instr_SLLW,
    Instr_SLLIW,
    Instr_SRA,
    Instr_SRAW,
    Instr_SRAI,
    Instr_SRAIW,
    Instr_SRL,
    Instr_SRLI,
    Instr_SRLIW,
    Instr_SRLW,
    Instr_SB,
    Instr_SH,
    Instr_SW,
    Instr_SD,
    Instr_SUB,
    Instr_SUBW,
    Instr_XOR,
    Instr_XORI,
    Instr_CSRRW,
    Instr_CSRRS,
    Instr_CSRRC,
    Instr_CSRRWI,
    Instr_CSRRCI,
    Instr_CSRRSI,
    Instr_URET,
    Instr_SRET,
    Instr_HRET,
    Instr_MRET,
    Instr_FENCE,
    Instr_FENCE_I,
    Instr_DIV,
    Instr_DIVU,
    Instr_DIVW,
    Instr_DIVUW,
    Instr_MUL,
    Instr_MULW,
    Instr_REM,
    Instr_REMU,
    Instr_REMW,
    Instr_REMUW,
    Instr_ECALL,
    Instr_EBREAK,
 
    Instr_Total
};
 
}  // namespace debugger
 
#endif  // __DEBUGGER_RIVER_CFG_H__