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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [WRITE_SEG.v] - Rev 2

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//=============================================================================
//  2009,2010 Robert Finch
//  Stratford
//  eq<remove>@birdcomputer.ca
//
//  WRITE_SEG state
//  - update the segment register
//
//
//	NO WARRANTY.
//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
//	EXPRESS OR IMPLIED. The user must assume the entire risk of using the
//	Work.
//
//	IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
//	IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
//	IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
//	REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
//	LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
//	AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
//	LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//=============================================================================
//
// Write to segment register
//
WRITE_SEG:
	begin
		state <= IFETCH;
		case(rrr)
		3'd0:	es <= res;
		3'd1:	cs <= res;
		3'd2:	ss <= res;
		3'd3:	ds <= res;
		default:	;
		endcase
	end
 

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