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// ============================================================================
//        __
//   \\__/ o\    (C) 2016-2017  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//
//	SyncGen640x400_70Hz.v
//		sync generator
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
//
//	WXGA video sync generator.
//
//	Input clock:     25.00 MHz (100 MHz * 2/8)
//	Horizontal freq: 31.25 kHz (generated) (31.250KHz)
//	Vertical freq:   69.60  Hz (generated) (69.599 Hz)
//
//	This module generates the basic sync timing signals required for a
//	WXGA display.
//
// ============================================================================
 
module SyncGen640x400_70Hz(rst, clk, hSync, vSync, hCtr, vCtr, blank, border, csel, rsel);
parameter phSyncOn  = 8;		//   8 front porch
parameter phSyncOff = 104;		//  96 sync
parameter phBlankOff = 144;		//  40 back porch
parameter phBorderOff = 152;	//   8 border
parameter phBorderOn = 792;		// 640 display
parameter phBorderOff2 = 168;
parameter phBorderOn2 = 776;
parameter phBlankOn = 800;		//    8 border
parameter phTotal = 800;		// 800 total clocks
//
parameter pvSyncOn  = 5;		//    5 front porch
parameter pvSyncOff = 7;		//    2 vertical sync
parameter pvBlankOff = 35;		//   28 back porch
parameter pvBorderOff = 42;		//    7 border	0
parameter pvBorderOn = 442;		//  400 display
parameter pvBorderOff2 = 50;
parameter pvBorderOn2 = 434;
parameter pvBlankOn = 449;  	//    7 border	0
parameter pvTotal = 449;		//  449 total scan lines
// 70 Hz
// 640x400
input rst;			// reset
input clk;			// video clock
output reg hSync, vSync;	// sync outputs
output [9:0] hCtr;
output [9:0] vCtr;
output blank;			// blanking output
output border;
input csel;			// column select
input rsel;			// row select
 
//---------------------------------------------------------------------
//---------------------------------------------------------------------
 
wire vBlank, hBlank;
wire vBorder,hBorder;
wire hSync1,vSync1;
reg blank;
reg border;
 
wire eol = hCtr==phTotal;
wire eof = vCtr==pvTotal && eol;
 
assign vSync1 = vCtr >= pvSyncOn && vCtr < pvSyncOff;
assign hSync1 = !(hCtr >= phSyncOn && hCtr < phSyncOff);
assign vBlank = vCtr >= pvBlankOn || vCtr < pvBlankOff;
assign hBlank = hCtr >= phBlankOn || hCtr < phBlankOff;
wire vBorder1 = vCtr >= pvBorderOn || vCtr < pvBorderOff;
wire hBorder1 = hCtr >= phBorderOn || hCtr < phBorderOff;
wire vBorder2 = vCtr >= pvBorderOn2 || vCtr < pvBorderOff2;
wire hBorder2 = hCtr >= phBorderOn2 || hCtr < phBorderOff2;
assign vBorder = rsel ? vBorder2 : vBorder1;
assign hBorder = csel ? hBorder2 : hBorder1;
 
counter #(10) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(eol), .d(12'd1), .q(hCtr), .tc() );
counter #(10) u2 (.rst(rst), .clk(clk), .ce(eol),  .ld(eof), .d(12'd1), .q(vCtr), .tc() );
 
always @(posedge clk)
    blank <= #1 hBlank|vBlank;
always @(posedge clk)
    border <= #1 hBorder|vBorder;
always @(posedge clk)
	hSync <= #1 hSync1;
always @(posedge clk)
	vSync <= #1 vSync1;
 
endmodule