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// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//
//	delay.v
//		- delays signals by so many clock cycles
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
//    contributors may be used to endorse or promote products derived from
//    this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//                                                                          
// ============================================================================
//
module delay1
	#(parameter WID = 1)
	(
	input clk,
	input ce,
	input [WID:1] i,
	output reg [WID:1] o
	);
 
	always @(posedge clk)
		if (ce)
			o <= i;
 
endmodule
 
 
module delay2
	#(parameter WID = 1)
	(
	input clk,
	input ce,
	input [WID:1] i,
	output reg [WID:1] o
	);
 
 
	reg	[WID:1]	r1;
 
	always @(posedge clk)
		if (ce)
			r1 <= i;
 
	always @(posedge clk)
		if (ce)
			o <= r1;
 
endmodule
 
 
module delay3
	#(parameter WID = 1)
	(
	input clk,
	input ce,
	input [WID:1] i,
	output reg [WID:1] o
	);
 
	reg	[WID:1] r1, r2;
 
	always @(posedge clk)
		if (ce)
			r1 <= i;
 
	always @(posedge clk)
		if (ce)
			r2 <= r1;
 
	always @(posedge clk)
		if (ce)
			o <= r2;
 
endmodule
 
module delay4
	#(parameter WID = 1)
	(
	input clk,
	input ce,
	input [WID-1:0] i,
	output reg [WID-1:0] o
	);
 
	reg	[WID-1:0] r1, r2, r3;
 
	always @(posedge clk)
		if (ce)
			r1 <= i;
 
	always @(posedge clk)
		if (ce)
			r2 <= r1;
 
	always @(posedge clk)
		if (ce)
			r3 <= r2;
 
	always @(posedge clk)
		if (ce)
			o <= r3;
 
endmodule
 
 
module delay5
#(parameter WID = 1)
(
	input clk,
	input ce,
	input [WID:1] i,
	output reg [WID:1] o
);
 
	reg	[WID:1] r1, r2, r3, r4;
 
	always @(posedge clk)
		if (ce) r1 <= i;
 
	always @(posedge clk)
		if (ce) r2 <= r1;
 
	always @(posedge clk)
		if (ce) r3 <= r2;
 
	always @(posedge clk)
		if (ce) r4 <= r3;
 
	always @(posedge clk)
		if (ce) o <= r4;
 
endmodule
 
module delay6
#(parameter WID = 1)
(
	input clk,
	input ce,
	input [WID:1] i,
	output reg [WID:1] o
);
 
	reg	[WID:1] r1, r2, r3, r4, r5;
 
	always @(posedge clk)
		if (ce) r1 <= i;
 
	always @(posedge clk)
		if (ce) r2 <= r1;
 
	always @(posedge clk)
		if (ce) r3 <= r2;
 
	always @(posedge clk)
		if (ce) r4 <= r3;
 
	always @(posedge clk)
		if (ce) r5 <= r4;
 
	always @(posedge clk)
		if (ce) o <= r5;
 
endmodule
 
module delay(clk, ce, i, o);
parameter WID = 1;
parameter DEP = 1;
input clk;
input ce;
input [WID-1:0] i;
output [WID-1:0] o;
 
reg [WID-1:0] pldreg [0:DEP-1];
 
genvar g;
generate begin : gPipeline
  always @(posedge clk)
    if (ce) pldreg[0] <= i;
  for (g = 0; g < DEP - 1; g = g + 1)
    always @(posedge clk)
      if (ce) pldreg[g+1] <= pldreg[g];
  assign o = pldreg[DEP-1];    
end
endgenerate
 
endmodule