URL
https://opencores.org/ocsvn/scarts/scarts/trunk
Subversion Repositories scarts
[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [mul.cgs] - Rev 26
Compare with Previous | Blame | View Log
# fr30 testcase for mul $Rj,$Ri# mach(): fr30.include "testutils.inc"START.text.global mulmul:; Test mul $Rj,$Ri; Positive operandsmvi_h_gr 3,r7 ; multiply small numbersmvi_h_gr 2,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 6,mdlmvi_h_gr 1,r7 ; multiply by 1mvi_h_gr 2,r8set_cc 0x0e ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 0test_h_dr 0,mdhtest_h_dr 2,mdlmvi_h_gr 2,r7 ; multiply by 1mvi_h_gr 1,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 2,mdlmvi_h_gr 0,r7 ; multiply by 0mvi_h_gr 2,r8set_cc 0x0b ; Set mask opposite of expectedmul r7,r8test_cc 0 1 0 1test_h_dr 0,mdhtest_h_dr 0,mdlmvi_h_gr 2,r7 ; multiply by 0mvi_h_gr 0,r8set_cc 0x0a ; Set mask opposite of expectedmul r7,r8test_cc 0 1 0 0test_h_dr 0,mdhtest_h_dr 0,mdlmvi_h_gr 0x3fffffff,r7 ; 31 bit resultmvi_h_gr 2,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 0x7ffffffe,mdlmvi_h_gr 0x40000000,r7 ; 32 bit resultmvi_h_gr 2,r8set_cc 0x04 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 1 0test_h_dr 0,mdhtest_h_dr 0x80000000,mdlmvi_h_gr 0x40000000,r7 ; 33 bit resultmvi_h_gr 4,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 1,mdhtest_h_dr 0x00000000,mdlmvi_h_gr 0x7fffffff,r7 ; max positive resultmvi_h_gr 0x7fffffff,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 0x3fffffff,mdhtest_h_dr 0x00000001,mdl; Mixed operandsmvi_h_gr -3,r7 ; multiply small numbersmvi_h_gr 2,r8set_cc 0x07 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 1test_h_dr -1,mdhtest_h_dr -6,mdlmvi_h_gr 3,r7 ; multiply small numbersmvi_h_gr -2,r8set_cc 0x07 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 1test_h_dr -1,mdhtest_h_dr -6,mdlmvi_h_gr 1,r7 ; multiply by 1mvi_h_gr -2,r8set_cc 0x06 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 0test_h_dr -1,mdhtest_h_dr -2,mdlmvi_h_gr -2,r7 ; multiply by 1mvi_h_gr 1,r8set_cc 0x07 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 1test_h_dr -1,mdhtest_h_dr -2,mdlmvi_h_gr 0,r7 ; multiply by 0mvi_h_gr -2,r8set_cc 0x0b ; Set mask opposite of expectedmul r7,r8test_cc 0 1 0 1test_h_dr 0,mdhtest_h_dr 0,mdlmvi_h_gr -2,r7 ; multiply by 0mvi_h_gr 0,r8set_cc 0x0a ; Set mask opposite of expectedmul r7,r8test_cc 0 1 0 0test_h_dr 0,mdhtest_h_dr 0,mdlmvi_h_gr 0x20000001,r7 ; 31 bit resultmvi_h_gr -2,r8set_cc 0x07 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 1test_h_dr 0xffffffff,mdhtest_h_dr 0xbffffffe,mdlmvi_h_gr 0x40000000,r7 ; 32 bit resultmvi_h_gr -2,r8set_cc 0x06 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 0 0test_h_dr 0xffffffff,mdhtest_h_dr 0x80000000,mdlmvi_h_gr 0x40000001,r7 ; 32 bit resultmvi_h_gr -2,r8set_cc 0x0c ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 0test_h_dr 0xffffffff,mdhtest_h_dr 0x7ffffffe,mdlmvi_h_gr 0x40000000,r7 ; 33 bit resultmvi_h_gr -4,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 0xffffffff,mdhtest_h_dr 0x00000000,mdlmvi_h_gr 0x7fffffff,r7 ; max negative resultmvi_h_gr 0x80000000,r8set_cc 0x05 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 1 1test_h_dr 0xc0000000,mdhtest_h_dr 0x80000000,mdl; Negative operandsmvi_h_gr -3,r7 ; multiply small numbersmvi_h_gr -2,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 6,mdlmvi_h_gr -1,r7 ; multiply by 1mvi_h_gr -2,r8set_cc 0x0e ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 0test_h_dr 0,mdhtest_h_dr 2,mdlmvi_h_gr -2,r7 ; multiply by 1mvi_h_gr -1,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 2,mdlmvi_h_gr 0xc0000001,r7 ; 31 bit resultmvi_h_gr -2,r8set_cc 0x0f ; Set mask opposite of expectedmul r7,r8test_cc 0 0 0 1test_h_dr 0,mdhtest_h_dr 0x7ffffffe,mdlmvi_h_gr 0xc0000000,r7 ; 32 bit resultmvi_h_gr -2,r8set_cc 0x04 ; Set mask opposite of expectedmul r7,r8test_cc 1 0 1 0test_h_dr 0,mdhtest_h_dr 0x80000000,mdlmvi_h_gr 0xc0000000,r7 ; 33 bit resultmvi_h_gr -4,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 1,mdhtest_h_dr 0x00000000,mdlmvi_h_gr 0x80000001,r7 ; almost max positive resultmvi_h_gr 0x80000001,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 0x3fffffff,mdhtest_h_dr 0x00000001,mdlmvi_h_gr 0x80000000,r7 ; max positive resultmvi_h_gr 0x80000000,r8set_cc 0x0d ; Set mask opposite of expectedmul r7,r8test_cc 0 0 1 1test_h_dr 0x40000000,mdhtest_h_dr 0x00000000,mdlpass