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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr500/] [cmqsubhss.cgs] - Rev 26
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# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond# mach: frv fr500.include "../testutils.inc"start.global msubhssmsubhss:set_spr_immed 0x1b1b,cccrset_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc0,1test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0xdead,0x4111,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc0,1test_fr_limmed 0x4111,0xdead,fr14test_fr_limmed 0x0123,0x4567,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc0,1test_fr_limmed 0x1235,0x5679,fr14test_fr_limmed 0x7fff,0x7fff,fr15test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc4,1test_fr_limmed 0x8000,0x8000,fr14test_fr_limmed 0x8000,0x8000,fr15test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc4,1cmqsubhss fr12,fr10,fr16,cc4,1test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0x0000,0x0000,fr15test_fr_limmed 0x8000,0x8000,fr16test_fr_limmed 0x8001,0x8001,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc1,0test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0xdead,0x4111,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc1,0test_fr_limmed 0x4111,0xdead,fr14test_fr_limmed 0x0123,0x4567,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc1,0test_fr_limmed 0x1235,0x5679,fr14test_fr_limmed 0x7fff,0x7fff,fr15test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc5,0test_fr_limmed 0x8000,0x8000,fr14test_fr_limmed 0x8000,0x8000,fr15test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc5,0cmqsubhss fr12,fr10,fr16,cc5,0test_fr_limmed 0x0000,0x0000,fr14test_fr_limmed 0x0000,0x0000,fr15test_fr_limmed 0x8000,0x8000,fr16test_fr_limmed 0x8001,0x8001,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc0,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc0,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc0,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc4,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc4,0cmqsubhss fr12,fr10,fr16,cc4,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc1,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc1,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc1,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc5,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc5,1cmqsubhss fr12,fr10,fr16,cc5,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc2,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc2,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc2,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc6,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc6,1cmqsubhss fr12,fr10,fr16,cc6,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1111,0x1111,fr14set_fr_iimmed 0x2222,0x2222,fr15set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0xdead,0x0000,fr11set_fr_iimmed 0x0000,0x0000,fr12set_fr_iimmed 0x0000,0xbeef,fr13cmqsubhss fr10,fr12,fr14,cc3,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0x1234,0x5678,fr11set_fr_iimmed 0xbeef,0x0000,fr12set_fr_iimmed 0x1111,0x1111,fr13cmqsubhss fr10,fr12,fr14,cc3,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x7ffe,0x7ffe,fr11set_fr_iimmed 0xffff,0xffff,fr12set_fr_iimmed 0xfffe,0xffff,fr13cmqsubhss fr10,fr12,fr14,cc3,1test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8001,0x8001,fr11set_fr_iimmed 0x0001,0x0002,fr12set_fr_iimmed 0x0002,0x0001,fr13cmqsubhss fr10,fr12,fr14,cc7,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x3333,0x3333,fr16set_fr_iimmed 0x4444,0x4444,fr17set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0xffff,0xffff,fr11set_fr_iimmed 0x8000,0x8000,fr12set_fr_iimmed 0x8000,0x8000,fr13cmqsubhss.p fr10,fr10,fr14,cc7,1cmqsubhss fr12,fr10,fr16,cc7,0test_fr_limmed 0x1111,0x1111,fr14test_fr_limmed 0x2222,0x2222,fr15test_fr_limmed 0x3333,0x3333,fr16test_fr_limmed 0x4444,0x4444,fr17test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setpass