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-- SDHC-SC-Core
-- Secure Digital High Capacity Self Configuring Core
-- 
-- (C) Copyright 2010, Rainer Kastl
-- All rights reserved.
-- 
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
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--     * Neither the name of the <organization> nor the
--       names of its contributors may be used to endorse or promote products
--       derived from this software without specific prior written permission.
-- 
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS  "AS IS" AND
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-- 
-- File        : SinglePortedRam-Rtl-a.vhdl
-- Owner       : Rainer Kastl
-- Description : 
-- Links       : 
-- 
 
architecture Rtl of SinglePortedRam is
 
	subtype aWord is std_ulogic_vector(gDataWidth - 1 downto 0);
	type aMemory is array (0 to 2**gAddrWidth - 1) of aWord;
 
	signal memory : aMemory := (others => (others => '0'));
 
begin
 
	SinglePort : process (iClk)
	begin
		if (iClk'event and iClk = '1') then
			if (iWe = '1') then
				memory(iAddr) <= iData;
 
				oData <= iData;
			else
				oData <= memory(iAddr);
			end if;
		end if;
	end process SinglePort;
 
end architecture Rtl;