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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [sgmii.html] - Rev 9

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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - Triple Speed Ethernet MegaCore Function v11.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altera_tse_pcs_pma_gige</TD></TR><TR><TD><B>Variation Name</B></TD><TD>sgmii</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>D:\JEFF\OpenCores\SGMII\trunk\sim\BFMs\SGMII_altera</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>sgmii.v</TD><TD>A MegaCore<small><sup>&reg</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function.  Instantiate the entity defined by this file inside of  your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>sgmii_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function  variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>sgmii.bsf</TD><TD>Quartus<small><sup>&reg</sup></small> II symbol file for the MegaCore function variation.  You can use this file in the Quartus  II block diagram editor.</TD></TR><TR><TD>sgmii.vo</TD><TD>Verilog HDL IP functional simulation model</TD></TR><TR><TD>sgmii.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>sgmii.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>gmii_rx_d</TD><TD>OUTPUT</TD><TD>8</TD></TR><TR><TD>gmii_rx_dv</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>gmii_rx_err</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>gmii_tx_d</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>gmii_tx_en</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>gmii_tx_err</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>tx_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rx_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mii_rx_d</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>mii_rx_dv</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mii_rx_err</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mii_tx_d</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>mii_tx_en</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mii_tx_err</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mii_col</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mii_crs</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>set_10</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>set_100</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>set_1000</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>hd_ena</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>reset_tx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_rx_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>led_col</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>led_crs</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>led_an</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>led_disp_err</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>led_char_err</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>led_link</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tx_clkena</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rx_clkena</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rx_recovclkout</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>address</TD><TD>INPUT</TD><TD>5</TD></TR><TR><TD>readdata</TD><TD>OUTPUT</TD><TD>16</TD></TR><TR><TD>read</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>writedata</TD><TD>INPUT</TD><TD>16</TD></TR><TR><TD>write</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>waitrequest</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>txp</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rxp</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>gxb_pwrdn_in</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pcs_pwrdn_out</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>gxb_cal_blk_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reconfig_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reconfig_togxb</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>reconfig_fromgxb</TD><TD>OUTPUT</TD><TD>17</TD></TR><TR><TD>reconfig_busy</TD><TD>INPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>

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