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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_alt4gxb_gige_wo_rmfifo.v] - Rev 9
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// megafunction wizard: %ALTGX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: alt4gxb // ============================================================ // File Name: altera_tse_alt4gxb_gige_wo_rmfifo.v // Megafunction Name(s): // alt4gxb // // Simulation Library Files(s): // stratixiv_hssi // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 11.0 Internal Build 138 03/15/2011 PN Full Version // ************************************************************ //Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset //VERSION_BEGIN 11.0 cbx_alt4gxb 2011:03:15:21:10:44:PN cbx_mgl 2011:03:15:21:50:29:PN cbx_tgx 2011:03:15:21:10:44:PN VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on (* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=c104"} *) module altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_nmca ( cal_blk_clk, fixedclk, fixedclk_fast, gxb_powerdown, pll_inclk, pll_locked, pll_powerdown, reconfig_clk, reconfig_fromgxb, reconfig_togxb, rx_analogreset, rx_clkout, rx_cruclk, rx_ctrldetect, rx_datain, rx_dataout, rx_digitalreset, rx_disperr, rx_errdetect, rx_freqlocked, rx_patterndetect, rx_recovclkout, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_seriallpbken, rx_syncstatus, tx_clkout, tx_ctrlenable, tx_datain, tx_dataout, tx_digitalreset) /* synthesis synthesis_clearbox=2 */; input cal_blk_clk; input fixedclk; input [5:0] fixedclk_fast; input [0:0] gxb_powerdown; input pll_inclk; output [0:0] pll_locked; input [0:0] pll_powerdown; input reconfig_clk; output [16:0] reconfig_fromgxb; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; output [0:0] rx_clkout; input [0:0] rx_cruclk; output [0:0] rx_ctrldetect; input [0:0] rx_datain; output [7:0] rx_dataout; input [0:0] rx_digitalreset; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_freqlocked; output [0:0] rx_patterndetect; output [0:0] rx_recovclkout; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; input [0:0] rx_seriallpbken; output [0:0] rx_syncstatus; output [0:0] tx_clkout; input [0:0] tx_ctrlenable; input [7:0] tx_datain; output [0:0] tx_dataout; input [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 cal_blk_clk; tri0 fixedclk; tri1 [5:0] fixedclk_fast; tri0 [0:0] gxb_powerdown; tri0 pll_inclk; tri0 [0:0] pll_powerdown; tri0 reconfig_clk; tri0 [0:0] rx_analogreset; tri0 [0:0] rx_cruclk; tri0 [0:0] rx_digitalreset; tri0 [0:0] rx_seriallpbken; tri0 [0:0] tx_ctrlenable; tri0 [7:0] tx_datain; tri0 [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif parameter starting_channel_number = 0; reg fixedclk_div0quad0c; wire wire_fixedclk_div0quad0c_clk; reg fixedclk_div1quad0c; wire wire_fixedclk_div1quad0c_clk; reg fixedclk_div2quad0c; wire wire_fixedclk_div2quad0c_clk; reg fixedclk_div3quad0c; wire wire_fixedclk_div3quad0c_clk; reg fixedclk_div4quad0c; wire wire_fixedclk_div4quad0c_clk; reg fixedclk_div5quad0c; wire wire_fixedclk_div5quad0c_clk; reg [1:0] reconfig_togxb_busy_reg; wire wire_cal_blk0_nonusertocmu; wire [1:0] wire_ch_clk_div0_analogfastrefclkout; wire [1:0] wire_ch_clk_div0_analogrefclkout; wire wire_ch_clk_div0_analogrefclkpulse; wire [99:0] wire_ch_clk_div0_dprioout; wire [599:0] wire_cent_unit0_cmudividerdprioout; wire [1799:0] wire_cent_unit0_cmuplldprioout; wire wire_cent_unit0_dpriodisableout; wire wire_cent_unit0_dprioout; wire [1:0] wire_cent_unit0_pllpowerdn; wire [1:0] wire_cent_unit0_pllresetout; wire wire_cent_unit0_quadresetout; wire [5:0] wire_cent_unit0_rxanalogresetout; wire [5:0] wire_cent_unit0_rxcrupowerdown; wire [5:0] wire_cent_unit0_rxcruresetout; wire [3:0] wire_cent_unit0_rxdigitalresetout; wire [5:0] wire_cent_unit0_rxibpowerdown; wire [1599:0] wire_cent_unit0_rxpcsdprioout; wire [1799:0] wire_cent_unit0_rxpmadprioout; wire [5:0] wire_cent_unit0_txanalogresetout; wire [3:0] wire_cent_unit0_txctrlout; wire [31:0] wire_cent_unit0_txdataout; wire [5:0] wire_cent_unit0_txdetectrxpowerdown; wire [3:0] wire_cent_unit0_txdigitalresetout; wire [5:0] wire_cent_unit0_txobpowerdown; wire [599:0] wire_cent_unit0_txpcsdprioout; wire [1799:0] wire_cent_unit0_txpmadprioout; wire [3:0] wire_rx_cdr_pll0_clk; wire [1:0] wire_rx_cdr_pll0_dataout; wire [299:0] wire_rx_cdr_pll0_dprioout; wire wire_rx_cdr_pll0_freqlocked; wire wire_rx_cdr_pll0_locked; wire wire_rx_cdr_pll0_pfdrefclkout; wire [3:0] wire_tx_pll0_clk; wire [299:0] wire_tx_pll0_dprioout; wire wire_tx_pll0_locked; wire wire_receive_pcs0_cdrctrllocktorefclkout; wire wire_receive_pcs0_clkout; wire [3:0] wire_receive_pcs0_ctrldetect; wire [39:0] wire_receive_pcs0_dataout; wire [3:0] wire_receive_pcs0_disperr; wire [399:0] wire_receive_pcs0_dprioout; wire [3:0] wire_receive_pcs0_errdetect; wire [3:0] wire_receive_pcs0_patterndetect; wire wire_receive_pcs0_rlv; wire [3:0] wire_receive_pcs0_rmfifodatadeleted; wire [3:0] wire_receive_pcs0_rmfifodatainserted; wire [3:0] wire_receive_pcs0_runningdisp; wire [3:0] wire_receive_pcs0_syncstatus; wire [7:0] wire_receive_pma0_analogtestbus; wire wire_receive_pma0_clockout; wire wire_receive_pma0_dataout; wire [299:0] wire_receive_pma0_dprioout; wire wire_receive_pma0_locktorefout; wire [63:0] wire_receive_pma0_recoverdataout; wire wire_receive_pma0_signaldetect; wire wire_transmit_pcs0_clkout; wire [19:0] wire_transmit_pcs0_dataout; wire [149:0] wire_transmit_pcs0_dprioout; wire wire_transmit_pcs0_forceelecidleout; wire wire_transmit_pcs0_txdetectrx; wire wire_transmit_pma0_clockout; wire wire_transmit_pma0_dataout; wire [299:0] wire_transmit_pma0_dprioout; wire wire_transmit_pma0_seriallpbkout; wire [1:0] analogfastrefclkout; wire [1:0] analogrefclkout; wire [0:0] analogrefclkpulse; wire cal_blk_powerdown; wire [599:0] cent_unit_cmudividerdprioout; wire [1799:0] cent_unit_cmuplldprioout; wire [1:0] cent_unit_pllpowerdn; wire [1:0] cent_unit_pllresetout; wire [0:0] cent_unit_quadresetout; wire [5:0] cent_unit_rxcrupowerdn; wire [5:0] cent_unit_rxibpowerdn; wire [1599:0] cent_unit_rxpcsdprioin; wire [1599:0] cent_unit_rxpcsdprioout; wire [1799:0] cent_unit_rxpmadprioin; wire [1799:0] cent_unit_rxpmadprioout; wire [1199:0] cent_unit_tx_dprioin; wire [31:0] cent_unit_tx_xgmdataout; wire [3:0] cent_unit_txctrlout; wire [5:0] cent_unit_txdetectrxpowerdn; wire [599:0] cent_unit_txdprioout; wire [5:0] cent_unit_txobpowerdn; wire [1799:0] cent_unit_txpmadprioin; wire [1799:0] cent_unit_txpmadprioout; wire [599:0] clk_div_cmudividerdprioin; wire [5:0] fixedclk_div_in; wire [0:0] fixedclk_enable; wire [5:0] fixedclk_in; wire [0:0] fixedclk_sel; wire [5:0] fixedclk_to_cmu; wire [0:0] nonusertocmu_out; wire [9:0] pll0_clkin; wire [299:0] pll0_dprioin; wire [299:0] pll0_dprioout; wire [3:0] pll0_out; wire [1:0] pll_ch_dataout_wire; wire [299:0] pll_ch_dprioout; wire [1799:0] pll_cmuplldprioout; wire [0:0] pll_inclk_wire; wire [0:0] pll_locked_out; wire [1:0] pllpowerdn_in; wire [1:0] pllreset_in; wire [0:0] reconfig_togxb_busy; wire [0:0] reconfig_togxb_disable; wire [0:0] reconfig_togxb_in; wire [0:0] reconfig_togxb_load; wire [5:0] rx_analogreset_in; wire [5:0] rx_analogreset_out; wire [0:0] rx_clkout_wire; wire [0:0] rx_coreclk_in; wire [9:0] rx_cruclk_in; wire [3:0] rx_deserclock_in; wire [3:0] rx_digitalreset_in; wire [3:0] rx_digitalreset_out; wire [0:0] rx_enapatternalign; wire [0:0] rx_freqlocked_wire; wire [0:0] rx_locktodata; wire [0:0] rx_locktodata_wire; wire [0:0] rx_locktorefclk; wire [0:0] rx_locktorefclk_wire; wire [7:0] rx_out_wire; wire [1599:0] rx_pcsdprioin_wire; wire [1599:0] rx_pcsdprioout; wire [0:0] rx_phfifordenable; wire [0:0] rx_phfiforeset; wire [0:0] rx_phfifowrdisable; wire [0:0] rx_pldcruclk_in; wire [3:0] rx_pll_clkout; wire [0:0] rx_pll_pfdrefclkout_wire; wire [0:0] rx_plllocked_wire; wire [16:0] rx_pma_analogtestbus; wire [0:0] rx_pma_clockout; wire [0:0] rx_pma_dataout; wire [0:0] rx_pma_locktorefout; wire [19:0] rx_pma_recoverdataout_wire; wire [1799:0] rx_pmadprioin_wire; wire [1799:0] rx_pmadprioout; wire [0:0] rx_powerdown; wire [5:0] rx_powerdown_in; wire [0:0] rx_prbscidenable; wire [5:0] rx_rxcruresetout; wire [1799:0] rxpll_dprioin; wire [5:0] tx_analogreset_out; wire [0:0] tx_clkout_int_wire; wire [0:0] tx_core_clkout_wire; wire [0:0] tx_coreclk_in; wire [7:0] tx_datain_wire; wire [19:0] tx_dataout_pcs_to_pma; wire [3:0] tx_digitalreset_in; wire [3:0] tx_digitalreset_out; wire [1199:0] tx_dprioin_wire; wire [0:0] tx_forcedisp_wire; wire [0:0] tx_invpolarity; wire [0:0] tx_localrefclk; wire [0:0] tx_phfiforeset; wire [1799:0] tx_pmadprioin_wire; wire [1799:0] tx_pmadprioout; wire [0:0] tx_serialloopbackout; wire [599:0] tx_txdprioout; wire [0:0] txdetectrxout; wire [0:0] w_cent_unit_dpriodisableout1w; // synopsys translate_off initial fixedclk_div0quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div0quad0c_clk) fixedclk_div0quad0c <= (~ fixedclk_div_in[0]); assign wire_fixedclk_div0quad0c_clk = fixedclk_in[0]; // synopsys translate_off initial fixedclk_div1quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div1quad0c_clk) fixedclk_div1quad0c <= (~ fixedclk_div_in[1]); assign wire_fixedclk_div1quad0c_clk = fixedclk_in[1]; // synopsys translate_off initial fixedclk_div2quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div2quad0c_clk) fixedclk_div2quad0c <= (~ fixedclk_div_in[2]); assign wire_fixedclk_div2quad0c_clk = fixedclk_in[2]; // synopsys translate_off initial fixedclk_div3quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div3quad0c_clk) fixedclk_div3quad0c <= (~ fixedclk_div_in[3]); assign wire_fixedclk_div3quad0c_clk = fixedclk_in[3]; // synopsys translate_off initial fixedclk_div4quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div4quad0c_clk) fixedclk_div4quad0c <= (~ fixedclk_div_in[4]); assign wire_fixedclk_div4quad0c_clk = fixedclk_in[4]; // synopsys translate_off initial fixedclk_div5quad0c = 0; // synopsys translate_on always @ ( posedge wire_fixedclk_div5quad0c_clk) fixedclk_div5quad0c <= (~ fixedclk_div_in[5]); assign wire_fixedclk_div5quad0c_clk = fixedclk_in[5]; // synopsys translate_off initial reconfig_togxb_busy_reg = 0; // synopsys translate_on always @ ( negedge fixedclk) reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy}; stratixiv_hssi_calibration_block cal_blk0 ( .calibrationstatus(), .clk(cal_blk_clk), .enabletestbus(1'b1), .nonusertocmu(wire_cal_blk0_nonusertocmu), .powerdn(cal_blk_powerdown) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .testctrl(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); stratixiv_hssi_clock_divider ch_clk_div0 ( .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout), .analogfastrefclkoutshifted(), .analogrefclkout(wire_ch_clk_div0_analogrefclkout), .analogrefclkoutshifted(), .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse), .analogrefclkpulseshifted(), .clk0in(pll0_out[3:0]), .coreclkout(), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(cent_unit_cmudividerdprioout[99:0]), .dprioout(wire_ch_clk_div0_dprioout), .quadreset(cent_unit_quadresetout[0]), .rateswitchbaseclock(), .rateswitchdone(), .rateswitchout(), .refclkout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1in({4{1'b0}}), .powerdn(1'b0), .rateswitch(1'b0), .rateswitchbaseclkin({2{1'b0}}), .rateswitchdonein({2{1'b0}}), .refclkdig(1'b0), .refclkin({2{1'b0}}), .vcobypassin(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4), ch_clk_div0.divide_by = 5, ch_clk_div0.divider_type = "CHANNEL_REGULAR", ch_clk_div0.effective_data_rate = "1250.0 Mbps", ch_clk_div0.enable_dynamic_divider = "false", ch_clk_div0.enable_refclk_out = "false", ch_clk_div0.inclk_select = 0, ch_clk_div0.logical_channel_address = (starting_channel_number + 0), ch_clk_div0.pre_divide_by = 1, ch_clk_div0.select_local_rate_switch_done = "false", ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0, ch_clk_div0.sim_analogrefclkout_phase_shift = 0, ch_clk_div0.sim_coreclkout_phase_shift = 0, ch_clk_div0.sim_refclkout_phase_shift = 0, ch_clk_div0.use_coreclk_out_post_divider = "false", ch_clk_div0.use_refclk_post_divider = "false", ch_clk_div0.use_vco_bypass = "false", ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider"; stratixiv_hssi_cmu cent_unit0 ( .adet({4{1'b0}}), .alignstatus(), .autospdx4configsel(), .autospdx4rateswitchout(), .autospdx4spdchg(), .clkdivpowerdn(), .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}), .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout), .cmuplldprioin(pll_cmuplldprioout[1799:0]), .cmuplldprioout(wire_cent_unit0_cmuplldprioout), .digitaltestout(), .dpclk(reconfig_clk), .dpriodisable(reconfig_togxb_disable), .dpriodisableout(wire_cent_unit0_dpriodisableout), .dprioin(reconfig_togxb_in), .dprioload(reconfig_togxb_load), .dpriooe(), .dprioout(wire_cent_unit0_dprioout), .enabledeskew(), .extra10gout(), .fiforesetrd(), .fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}), .lccmutestbus(), .nonuserfromcal(nonusertocmu_out[0]), .phfifiox4ptrsreset(), .pllpowerdn(wire_cent_unit0_pllpowerdn), .pllresetout(wire_cent_unit0_pllresetout), .quadreset(gxb_powerdown[0]), .quadresetout(wire_cent_unit0_quadresetout), .rdalign({4{1'b0}}), .rdenablesync(1'b0), .recovclk(1'b0), .refclkdividerdprioin({2{1'b0}}), .refclkdividerdprioout(), .rxadcepowerdown(), .rxadceresetout(), .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}), .rxanalogresetout(wire_cent_unit0_rxanalogresetout), .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown), .rxcruresetout(wire_cent_unit0_rxcruresetout), .rxctrl({4{1'b0}}), .rxctrlout(), .rxdatain({32{1'b0}}), .rxdataout(), .rxdatavalid({4{1'b0}}), .rxdigitalreset({rx_digitalreset_in[3:0]}), .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout), .rxibpowerdown(wire_cent_unit0_rxibpowerdown), .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}), .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout), .rxphfifox4byteselout(), .rxphfifox4rdenableout(), .rxphfifox4wrclkout(), .rxphfifox4wrenableout(), .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}), .rxpmadprioout(wire_cent_unit0_rxpmadprioout), .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}), .rxrunningdisp({4{1'b0}}), .scanout(), .syncstatus({4{1'b0}}), .testout(), .txanalogresetout(wire_cent_unit0_txanalogresetout), .txctrl({4{1'b0}}), .txctrlout(wire_cent_unit0_txctrlout), .txdatain({32{1'b0}}), .txdataout(wire_cent_unit0_txdataout), .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown), .txdigitalreset({tx_digitalreset_in[3:0]}), .txdigitalresetout(wire_cent_unit0_txdigitalresetout), .txdividerpowerdown(), .txobpowerdown(wire_cent_unit0_txobpowerdown), .txpcsdprioin({cent_unit_tx_dprioin[599:0]}), .txpcsdprioout(wire_cent_unit0_txpcsdprioout), .txphfifox4byteselout(), .txphfifox4rdclkout(), .txphfifox4rdenableout(), .txphfifox4wrenableout(), .txpllreset({{1{1'b0}}, pll_powerdown[0]}), .txpmadprioin({cent_unit_txpmadprioin[1799:0]}), .txpmadprioout(wire_cent_unit0_txpmadprioout) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .extra10gin({7{1'b0}}), .lccmurtestbussel({3{1'b0}}), .pmacramtest(1'b0), .rateswitch(1'b0), .rateswitchdonein(1'b0), .rxclk(1'b0), .rxcoreclk(1'b0), .rxphfifordenable(1'b1), .rxphfiforeset(1'b0), .rxphfifowrdisable(1'b0), .scanclk(1'b0), .scanin({23{1'b0}}), .scanmode(1'b0), .scanshift(1'b0), .testin({10000{1'b0}}), .txclk(1'b0), .txcoreclk(1'b0), .txphfiforddisable(1'b0), .txphfiforeset(1'b0), .txphfifowrenable(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8, cent_unit0.auto_spd_phystatus_notify_count = 0, cent_unit0.bonded_quad_mode = "none", cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1), cent_unit0.in_xaui_mode = "false", cent_unit0.offset_all_errors_align = "false", cent_unit0.pipe_auto_speed_nego_enable = "false", cent_unit0.pipe_freq_scale_mode = "Frequency", cent_unit0.pma_done_count = 249950, cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1), cent_unit0.rx0_auto_spd_self_switch_enable = "false", cent_unit0.rx0_channel_bonding = "none", cent_unit0.rx0_clk1_mux_select = "recovered clock", cent_unit0.rx0_clk2_mux_select = "recovered clock", cent_unit0.rx0_ph_fifo_reg_mode = "false", cent_unit0.rx0_rd_clk_mux_select = "core clock", cent_unit0.rx0_recovered_clk_mux_select = "recovered clock", cent_unit0.rx0_reset_clock_output_during_digital_reset = "false", cent_unit0.rx0_use_double_data_mode = "false", cent_unit0.tx0_auto_spd_self_switch_enable = "false", cent_unit0.tx0_channel_bonding = "none", cent_unit0.tx0_ph_fifo_reg_mode = "false", cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider", cent_unit0.tx0_use_double_data_mode = "false", cent_unit0.tx0_wr_clk_mux_select = "core_clk", cent_unit0.use_deskew_fifo = "false", cent_unit0.vcceh_voltage = "Auto", cent_unit0.lpm_type = "stratixiv_hssi_cmu"; stratixiv_hssi_pll rx_cdr_pll0 ( .areset(rx_rxcruresetout[0]), .clk(wire_rx_cdr_pll0_clk), .datain(rx_pma_dataout[0]), .dataout(wire_rx_cdr_pll0_dataout), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(rxpll_dprioin[299:0]), .dprioout(wire_rx_cdr_pll0_dprioout), .freqlocked(wire_rx_cdr_pll0_freqlocked), .inclk({rx_cruclk_in[9:0]}), .locked(wire_rx_cdr_pll0_locked), .locktorefclk(rx_pma_locktorefout[0]), .pfdfbclkout(), .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout), .powerdown(cent_unit_rxcrupowerdn[0]), .vcobypassout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .earlyeios(1'b0), .extra10gin({6{1'b0}}), .pfdfbclk(1'b0), .rateswitch(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam rx_cdr_pll0.bandwidth_type = "Medium", rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4), rx_cdr_pll0.dprio_config_mode = 6'h00, rx_cdr_pll0.effective_data_rate = "1250.0 Mbps", rx_cdr_pll0.enable_dynamic_divider = "false", rx_cdr_pll0.fast_lock_control = "false", rx_cdr_pll0.inclk0_input_period = 8000, rx_cdr_pll0.input_clock_frequency = "125.0 MHz", rx_cdr_pll0.m = 5, rx_cdr_pll0.n = 1, rx_cdr_pll0.pfd_clk_select = 0, rx_cdr_pll0.pll_type = "RX CDR", rx_cdr_pll0.use_refclk_pin = "false", rx_cdr_pll0.vco_post_scale = 4, rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll"; stratixiv_hssi_pll tx_pll0 ( .areset(pllreset_in[0]), .clk(wire_tx_pll0_clk), .dataout(), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(pll0_dprioin[299:0]), .dprioout(wire_tx_pll0_dprioout), .freqlocked(), .inclk({pll0_clkin[9:0]}), .locked(wire_tx_pll0_locked), .pfdfbclkout(), .pfdrefclkout(), .powerdown(pllpowerdn_in[0]), .vcobypassout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .datain(1'b0), .earlyeios(1'b0), .extra10gin({6{1'b0}}), .locktorefclk(1'b1), .pfdfbclk(1'b0), .rateswitch(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam tx_pll0.bandwidth_type = "High", tx_pll0.channel_num = 4, tx_pll0.dprio_config_mode = 6'h00, tx_pll0.inclk0_input_period = 8000, tx_pll0.input_clock_frequency = "125.0 MHz", tx_pll0.logical_tx_pll_number = 0, tx_pll0.m = 5, tx_pll0.n = 1, tx_pll0.pfd_clk_select = 0, tx_pll0.pfd_fb_select = "internal", tx_pll0.pll_type = "CMU", tx_pll0.use_refclk_pin = "false", tx_pll0.vco_post_scale = 4, tx_pll0.lpm_type = "stratixiv_hssi_pll"; stratixiv_hssi_rx_pcs receive_pcs0 ( .a1a2size(1'b0), .a1a2sizeout(), .a1detect(), .a2detect(), .adetectdeskew(), .alignstatus(1'b0), .alignstatussync(1'b0), .alignstatussyncout(), .autospdrateswitchout(), .autospdspdchgout(), .bistdone(), .bisterr(), .bitslipboundaryselectout(), .byteorderalignstatus(), .cdrctrlearlyeios(), .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])), .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout), .clkout(wire_receive_pcs0_clkout), .coreclk(rx_coreclk_in[0]), .coreclkout(), .ctrldetect(wire_receive_pcs0_ctrldetect), .datain(rx_pma_recoverdataout_wire[19:0]), .dataout(wire_receive_pcs0_dataout), .dataoutfull(), .digitalreset(rx_digitalreset_out[0]), .digitaltestout(), .disablefifordin(1'b0), .disablefifordout(), .disablefifowrin(1'b0), .disablefifowrout(), .disperr(wire_receive_pcs0_disperr), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(rx_pcsdprioin_wire[399:0]), .dprioout(wire_receive_pcs0_dprioout), .enabledeskew(1'b0), .enabyteord(1'b0), .enapatternalign(rx_enapatternalign[0]), .errdetect(wire_receive_pcs0_errdetect), .fifordin(1'b0), .fifordout(), .fiforesetrd(1'b0), .hipdataout(), .hipdatavalid(), .hipelecidle(), .hipphydonestatus(), .hipstatus(), .invpol(1'b0), .iqpphfifobyteselout(), .iqpphfifoptrsresetout(), .iqpphfifordenableout(), .iqpphfifowrclkout(), .iqpphfifowrenableout(), .k1detect(), .k2detect(), .localrefclk(1'b0), .masterclk(1'b0), .parallelfdbk({20{1'b0}}), .patterndetect(wire_receive_pcs0_patterndetect), .phfifobyteselout(), .phfifobyteserdisableout(), .phfifooverflow(), .phfifoptrsresetout(), .phfifordenable(rx_phfifordenable[0]), .phfifordenableout(), .phfiforeset(rx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrclkout(), .phfifowrdisable(rx_phfifowrdisable[0]), .phfifowrdisableout(), .phfifowrenableout(), .pipebufferstat(), .pipedatavalid(), .pipeelecidle(), .pipephydonestatus(), .pipepowerdown({2{1'b0}}), .pipepowerstate({4{1'b0}}), .pipestatetransdoneout(), .pipestatus(), .prbscidenable(rx_prbscidenable[0]), .quadreset(cent_unit_quadresetout[0]), .rateswitchout(), .rdalign(), .recoveredclk(rx_pma_clockout[0]), .revbitorderwa(1'b0), .revbyteorderwa(1'b0), .revparallelfdbkdata(), .rlv(wire_receive_pcs0_rlv), .rmfifoalmostempty(), .rmfifoalmostfull(), .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted), .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted), .rmfifoempty(), .rmfifofull(), .rmfifordena(1'b0), .rmfiforeset(1'b0), .rmfifowrena(1'b0), .runningdisp(wire_receive_pcs0_runningdisp), .rxdetectvalid(1'b0), .rxfound({2{1'b0}}), .signaldetect(), .syncstatus(wire_receive_pcs0_syncstatus), .syncstatusdeskew(), .xauidelcondmetout(), .xauififoovrout(), .xauiinsertincompleteout(), .xauilatencycompout(), .xgmctrldet(), .xgmctrlin(1'b0), .xgmdatain({8{1'b0}}), .xgmdataout(), .xgmdatavalid(), .xgmrunningdisp() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .autospdxnconfigsel({3{1'b0}}), .autospdxnspdchg({3{1'b0}}), .bitslip(1'b0), .elecidleinfersel({3{1'b0}}), .grayelecidleinferselfromtx({3{1'b0}}), .hip8b10binvpolarity(1'b0), .hipelecidleinfersel({3{1'b0}}), .hippowerdown({2{1'b0}}), .hiprateswitch(1'b0), .iqpautospdxnspgchg({2{1'b0}}), .iqpphfifoxnbytesel({2{1'b0}}), .iqpphfifoxnptrsreset({2{1'b0}}), .iqpphfifoxnrdenable({2{1'b0}}), .iqpphfifoxnwrclk({2{1'b0}}), .iqpphfifoxnwrenable({2{1'b0}}), .phfifox4bytesel(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrclk(1'b0), .phfifox4wrenable(1'b0), .phfifox8bytesel(1'b0), .phfifox8rdenable(1'b0), .phfifox8wrclk(1'b0), .phfifox8wrenable(1'b0), .phfifoxnbytesel({3{1'b0}}), .phfifoxnptrsreset({3{1'b0}}), .phfifoxnrdenable({3{1'b0}}), .phfifoxnwrclk({3{1'b0}}), .phfifoxnwrenable({3{1'b0}}), .pipe8b10binvpolarity(1'b0), .pipeenrevparallellpbkfromtx(1'b0), .pmatestbusin({8{1'b0}}), .powerdn({2{1'b0}}), .ppmdetectdividedclk(1'b0), .ppmdetectrefclk(1'b0), .rateswitch(1'b0), .rateswitchisdone(1'b0), .rateswitchxndone(1'b0), .refclk(1'b0), .rxelecidlerateswitch(1'b0), .signaldetected(1'b0), .wareset(1'b0), .xauidelcondmet(1'b0), .xauififoovr(1'b0), .xauiinsertincomplete(1'b0), .xauilatencycomp(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pcs0.align_pattern = "0101111100", receive_pcs0.align_pattern_length = 10, receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false", receive_pcs0.allow_align_polarity_inversion = "false", receive_pcs0.allow_pipe_polarity_inversion = "false", receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8, receive_pcs0.auto_spd_phystatus_notify_count = 0, receive_pcs0.auto_spd_self_switch_enable = "false", receive_pcs0.bit_slip_enable = "false", receive_pcs0.byte_order_double_data_mode_mask_enable = "false", receive_pcs0.byte_order_mode = "none", receive_pcs0.byte_order_pad_pattern = "0", receive_pcs0.byte_order_pattern = "0", receive_pcs0.byte_order_pld_ctrl_enable = "false", receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000, receive_pcs0.cdrctrl_enable = "false", receive_pcs0.cdrctrl_rxvalid_mask = "false", receive_pcs0.channel_bonding = "none", receive_pcs0.channel_number = ((starting_channel_number + 0) % 4), receive_pcs0.channel_width = 8, receive_pcs0.clk1_mux_select = "recovered clock", receive_pcs0.clk2_mux_select = "recovered clock", receive_pcs0.core_clock_0ppm = "false", receive_pcs0.datapath_low_latency_mode = "false", receive_pcs0.datapath_protocol = "basic", receive_pcs0.dec_8b_10b_compatibility_mode = "true", receive_pcs0.dec_8b_10b_mode = "normal", receive_pcs0.dec_8b_10b_polarity_inv_enable = "false", receive_pcs0.deskew_pattern = "0", receive_pcs0.disable_auto_idle_insertion = "true", receive_pcs0.disable_running_disp_in_word_align = "false", receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false", receive_pcs0.dprio_config_mode = 6'h01, receive_pcs0.elec_idle_infer_enable = "false", receive_pcs0.elec_idle_num_com_detect = 3, receive_pcs0.enable_bit_reversal = "false", receive_pcs0.enable_deep_align = "false", receive_pcs0.enable_deep_align_byte_swap = "false", receive_pcs0.enable_self_test_mode = "false", receive_pcs0.enable_true_complement_match_in_word_align = "false", receive_pcs0.force_signal_detect_dig = "true", receive_pcs0.hip_enable = "false", receive_pcs0.infiniband_invalid_code = 0, receive_pcs0.insert_pad_on_underflow = "false", receive_pcs0.logical_channel_address = (starting_channel_number + 0), receive_pcs0.num_align_code_groups_in_ordered_set = 1, receive_pcs0.num_align_cons_good_data = 4, receive_pcs0.num_align_cons_pat = 3, receive_pcs0.num_align_loss_sync_error = 4, receive_pcs0.ph_fifo_low_latency_enable = "true", receive_pcs0.ph_fifo_reg_mode = "false", receive_pcs0.ph_fifo_xn_mapping0 = "none", receive_pcs0.ph_fifo_xn_mapping1 = "none", receive_pcs0.ph_fifo_xn_mapping2 = "none", receive_pcs0.ph_fifo_xn_select = 1, receive_pcs0.pipe_auto_speed_nego_enable = "false", receive_pcs0.pipe_freq_scale_mode = "Frequency", receive_pcs0.pma_done_count = 249950, receive_pcs0.protocol_hint = "gige", receive_pcs0.rate_match_almost_empty_threshold = 11, receive_pcs0.rate_match_almost_full_threshold = 13, receive_pcs0.rate_match_back_to_back = "true", receive_pcs0.rate_match_delete_threshold = 13, receive_pcs0.rate_match_empty_threshold = 5, receive_pcs0.rate_match_fifo_mode = "false", receive_pcs0.rate_match_full_threshold = 20, receive_pcs0.rate_match_insert_threshold = 11, receive_pcs0.rate_match_ordered_set_based = "true", receive_pcs0.rate_match_pattern1 = "10100010010101111100", receive_pcs0.rate_match_pattern2 = "10101011011010000011", receive_pcs0.rate_match_pattern_size = 20, receive_pcs0.rate_match_reset_enable = "false", receive_pcs0.rate_match_skip_set_based = "false", receive_pcs0.rate_match_start_threshold = 7, receive_pcs0.rd_clk_mux_select = "core clock", receive_pcs0.recovered_clk_mux_select = "recovered clock", receive_pcs0.run_length = 5, receive_pcs0.run_length_enable = "true", receive_pcs0.rx_detect_bypass = "false", receive_pcs0.rx_phfifo_wait_cnt = 15, receive_pcs0.rxstatus_error_report_mode = 0, receive_pcs0.self_test_mode = "incremental", receive_pcs0.use_alignment_state_machine = "true", receive_pcs0.use_deserializer_double_data_mode = "false", receive_pcs0.use_deskew_fifo = "false", receive_pcs0.use_double_data_mode = "false", receive_pcs0.use_parallel_loopback = "false", receive_pcs0.use_rising_edge_triggered_pattern_align = "false", receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs"; stratixiv_hssi_rx_pma receive_pma0 ( .adaptdone(), .analogtestbus(wire_receive_pma0_analogtestbus), .clockout(wire_receive_pma0_clockout), .datain(rx_datain[0]), .dataout(wire_receive_pma0_dataout), .dataoutfull(), .deserclock(rx_deserclock_in[3:0]), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(rx_pmadprioin_wire[299:0]), .dprioout(wire_receive_pma0_dprioout), .freqlock(1'b0), .ignorephslck(1'b0), .locktodata(rx_locktodata_wire[0]), .locktoref(rx_locktorefclk_wire[0]), .locktorefout(wire_receive_pma0_locktorefout), .offsetcancellationen(1'b0), .plllocked(rx_plllocked_wire[0]), .powerdn(cent_unit_rxibpowerdn[0]), .ppmdetectclkrel(), .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]), .recoverdatain(pll_ch_dataout_wire[1:0]), .recoverdataout(wire_receive_pma0_recoverdataout), .reverselpbkout(), .revserialfdbkout(), .rxpmareset(rx_analogreset_out[0]), .seriallpbken(rx_seriallpbken[0]), .seriallpbkin(tx_serialloopbackout[0]), .signaldetect(wire_receive_pma0_signaldetect), .testbussel(4'b0110) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .adaptcapture(1'b0), .adcepowerdn(1'b0), .adcereset(1'b0), .adcestandby(1'b0), .extra10gin({38{1'b0}}), .ppmdetectdividedclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pma0.adaptive_equalization_mode = "none", receive_pma0.allow_serial_loopback = "true", receive_pma0.channel_number = ((starting_channel_number + 0) % 4), receive_pma0.channel_type = "auto", receive_pma0.common_mode = "0.82V", receive_pma0.deserialization_factor = 10, receive_pma0.dprio_config_mode = 6'h01, receive_pma0.enable_ltd = "false", receive_pma0.enable_ltr = "false", receive_pma0.eq_dc_gain = 0, receive_pma0.eqa_ctrl = 0, receive_pma0.eqb_ctrl = 0, receive_pma0.eqc_ctrl = 0, receive_pma0.eqd_ctrl = 0, receive_pma0.eqv_ctrl = 0, receive_pma0.eyemon_bandwidth = 0, receive_pma0.force_signal_detect = "true", receive_pma0.logical_channel_address = (starting_channel_number + 0), receive_pma0.low_speed_test_select = 0, receive_pma0.offset_cancellation = 1, receive_pma0.ppmselect = 32, receive_pma0.protocol_hint = "gige", receive_pma0.send_direct_reverse_serial_loopback = "None", receive_pma0.signal_detect_hysteresis = 2, receive_pma0.signal_detect_hysteresis_valid_threshold = 1, receive_pma0.signal_detect_loss_threshold = 1, receive_pma0.termination = "OCT 100 Ohms", receive_pma0.use_deser_double_data_width = "false", receive_pma0.use_external_termination = "false", receive_pma0.use_pma_direct = "false", receive_pma0.lpm_type = "stratixiv_hssi_rx_pma"; stratixiv_hssi_tx_pcs transmit_pcs0 ( .clkout(wire_transmit_pcs0_clkout), .coreclk(tx_coreclk_in[0]), .coreclkout(), .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}), .datain({{32{1'b0}}, tx_datain_wire[7:0]}), .datainfull({44{1'b0}}), .dataout(wire_transmit_pcs0_dataout), .detectrxloop(1'b0), .digitalreset(tx_digitalreset_out[0]), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(tx_dprioin_wire[149:0]), .dprioout(wire_transmit_pcs0_dprioout), .enrevparallellpbk(1'b0), .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}), .forcedispcompliance(1'b0), .forceelecidleout(wire_transmit_pcs0_forceelecidleout), .grayelecidleinferselout(), .hiptxclkout(), .invpol(tx_invpolarity[0]), .iqpphfifobyteselout(), .iqpphfifordclkout(), .iqpphfifordenableout(), .iqpphfifowrenableout(), .localrefclk(tx_localrefclk[0]), .parallelfdbkout(), .phfifobyteselout(), .phfifooverflow(), .phfifordclkout(), .phfiforddisable(1'b0), .phfiforddisableout(), .phfifordenableout(), .phfiforeset(tx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrenable(1'b1), .phfifowrenableout(), .pipeenrevparallellpbkout(), .pipepowerdownout(), .pipepowerstateout(), .pipestatetransdone(1'b0), .powerdn({2{1'b0}}), .quadreset(cent_unit_quadresetout[0]), .rateswitchout(), .rdenablesync(), .revparallelfdbk({20{1'b0}}), .txdetectrx(wire_transmit_pcs0_txdetectrx), .xgmctrl(cent_unit_txctrlout[0]), .xgmctrlenable(), .xgmdatain(cent_unit_tx_xgmdataout[7:0]), .xgmdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .bitslipboundaryselect({5{1'b0}}), .dispval({4{1'b0}}), .elecidleinfersel({3{1'b0}}), .forceelecidle(1'b0), .freezptr(1'b0), .hipdatain({10{1'b0}}), .hipdetectrxloop(1'b0), .hipelecidleinfersel({3{1'b0}}), .hipforceelecidle(1'b0), .hippowerdn({2{1'b0}}), .hiptxdeemph(1'b0), .hiptxmargin({3{1'b0}}), .iqpphfifoxnbytesel({2{1'b0}}), .iqpphfifoxnrdclk({2{1'b0}}), .iqpphfifoxnrdenable({2{1'b0}}), .iqpphfifoxnwrenable({2{1'b0}}), .phfifobyteserdisable(1'b0), .phfifoptrsreset(1'b0), .phfifox4bytesel(1'b0), .phfifox4rdclk(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrenable(1'b0), .phfifoxnbottombytesel(1'b0), .phfifoxnbottomrdclk(1'b0), .phfifoxnbottomrdenable(1'b0), .phfifoxnbottomwrenable(1'b0), .phfifoxnbytesel({3{1'b0}}), .phfifoxnptrsreset({3{1'b0}}), .phfifoxnrdclk({3{1'b0}}), .phfifoxnrdenable({3{1'b0}}), .phfifoxntopbytesel(1'b0), .phfifoxntoprdclk(1'b0), .phfifoxntoprdenable(1'b0), .phfifoxntopwrenable(1'b0), .phfifoxnwrenable({3{1'b0}}), .pipetxdeemph(1'b0), .pipetxmargin({3{1'b0}}), .pipetxswing(1'b0), .prbscidenable(1'b0), .rateswitch(1'b0), .rateswitchisdone(1'b0), .rateswitchxndone(1'b0), .refclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pcs0.allow_polarity_inversion = "false", transmit_pcs0.auto_spd_self_switch_enable = "false", transmit_pcs0.bitslip_enable = "false", transmit_pcs0.channel_bonding = "none", transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4), transmit_pcs0.channel_width = 8, transmit_pcs0.core_clock_0ppm = "false", transmit_pcs0.datapath_low_latency_mode = "false", transmit_pcs0.datapath_protocol = "basic", transmit_pcs0.disable_ph_low_latency_mode = "false", transmit_pcs0.disparity_mode = "none", transmit_pcs0.dprio_config_mode = 6'h01, transmit_pcs0.elec_idle_delay = 6, transmit_pcs0.enable_bit_reversal = "false", transmit_pcs0.enable_idle_selection = "true", transmit_pcs0.enable_reverse_parallel_loopback = "false", transmit_pcs0.enable_self_test_mode = "false", transmit_pcs0.enable_symbol_swap = "false", transmit_pcs0.enc_8b_10b_compatibility_mode = "true", transmit_pcs0.enc_8b_10b_mode = "normal", transmit_pcs0.force_echar = "false", transmit_pcs0.force_kchar = "false", transmit_pcs0.hip_enable = "false", transmit_pcs0.logical_channel_address = (starting_channel_number + 0), transmit_pcs0.ph_fifo_reg_mode = "false", transmit_pcs0.ph_fifo_xn_mapping0 = "none", transmit_pcs0.ph_fifo_xn_mapping1 = "none", transmit_pcs0.ph_fifo_xn_mapping2 = "none", transmit_pcs0.ph_fifo_xn_select = 1, transmit_pcs0.pipe_auto_speed_nego_enable = "false", transmit_pcs0.pipe_freq_scale_mode = "Frequency", transmit_pcs0.prbs_cid_pattern = "false", transmit_pcs0.protocol_hint = "gige", transmit_pcs0.refclk_select = "local", transmit_pcs0.self_test_mode = "incremental", transmit_pcs0.use_double_data_mode = "false", transmit_pcs0.use_serializer_double_data_mode = "false", transmit_pcs0.wr_clk_mux_select = "core_clk", transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs"; stratixiv_hssi_tx_pma transmit_pma0 ( .clockout(wire_transmit_pma0_clockout), .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}), .dataout(wire_transmit_pma0_dataout), .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]), .dftout(), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(tx_pmadprioin_wire[299:0]), .dprioout(wire_transmit_pma0_dprioout), .fastrefclk0in(analogfastrefclkout[1:0]), .fastrefclk1in({2{1'b0}}), .fastrefclk2in({2{1'b0}}), .fastrefclk4in({2{1'b0}}), .forceelecidle(1'b0), .powerdn(cent_unit_txobpowerdn[0]), .refclk0in({analogrefclkout[1:0]}), .refclk0inpulse(analogrefclkpulse[0]), .refclk1in({2{1'b0}}), .refclk1inpulse(1'b0), .refclk2in({2{1'b0}}), .refclk2inpulse(1'b0), .refclk4in({2{1'b0}}), .refclk4inpulse(1'b0), .revserialfdbk(1'b0), .rxdetecten(txdetectrxout[0]), .rxdetectvalidout(), .rxfoundout(), .seriallpbkout(wire_transmit_pma0_seriallpbkout), .txpmareset(tx_analogreset_out[0]) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .datainfull({20{1'b0}}), .extra10gin({11{1'b0}}), .fastrefclk3in({2{1'b0}}), .pclk({5{1'b0}}), .refclk3in({2{1'b0}}), .refclk3inpulse(1'b0), .rxdetectclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pma0.analog_power = "auto", transmit_pma0.channel_number = ((starting_channel_number + 0) % 4), transmit_pma0.channel_type = "auto", transmit_pma0.clkin_select = 0, transmit_pma0.clkmux_delay = "false", transmit_pma0.common_mode = "0.65V", transmit_pma0.dprio_config_mode = 6'h01, transmit_pma0.enable_reverse_serial_loopback = "false", transmit_pma0.logical_channel_address = (starting_channel_number + 0), transmit_pma0.logical_protocol_hint_0 = "gige", transmit_pma0.low_speed_test_select = 0, transmit_pma0.physical_clkin0_mapping = "x1", transmit_pma0.preemp_pretap = 0, transmit_pma0.preemp_pretap_inv = "false", transmit_pma0.preemp_tap_1 = 0, transmit_pma0.preemp_tap_2 = 0, transmit_pma0.preemp_tap_2_inv = "false", transmit_pma0.protocol_hint = "gige", transmit_pma0.rx_detect = 0, transmit_pma0.serialization_factor = 10, transmit_pma0.slew_rate = "medium", transmit_pma0.termination = "OCT 100 Ohms", transmit_pma0.use_external_termination = "false", transmit_pma0.use_pma_direct = "false", transmit_pma0.use_ser_double_data_mode = "false", transmit_pma0.vod_selection = 1, transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma"; assign analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout}, analogrefclkout = {wire_ch_clk_div0_analogrefclkout}, analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse}, cal_blk_powerdown = 1'b0, cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout}, cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout}, cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]}, cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]}, cent_unit_quadresetout = {wire_cent_unit0_quadresetout}, cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]}, cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]}, cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]}, cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]}, cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]}, cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]}, cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]}, cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]}, cent_unit_txctrlout = {wire_cent_unit0_txctrlout}, cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]}, cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]}, cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]}, cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]}, cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]}, clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout}, fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c}, fixedclk_enable = reconfig_togxb_busy_reg[0], fixedclk_in = {{5{1'b0}}, fixedclk}, fixedclk_sel = reconfig_togxb_busy_reg[1], fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))}, nonusertocmu_out = {wire_cal_blk0_nonusertocmu}, pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]}, pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]}, pll0_dprioout = {wire_tx_pll0_dprioout}, pll0_out = {wire_tx_pll0_clk[3:0]}, pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout}, pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout}, pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]}, pll_inclk_wire = {pll_inclk}, pll_locked = {pll_locked_out[0]}, pll_locked_out = {wire_tx_pll0_locked}, pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]}, pllreset_in = {1'b0, cent_unit_pllresetout[0]}, reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout}, reconfig_togxb_busy = reconfig_togxb[3], reconfig_togxb_disable = reconfig_togxb[1], reconfig_togxb_in = reconfig_togxb[0], reconfig_togxb_load = reconfig_togxb[2], rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])}, rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]}, rx_clkout = {rx_clkout_wire[0]}, rx_clkout_wire = {wire_receive_pcs0_clkout}, rx_coreclk_in = {rx_clkout_wire[0]}, rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]}, rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]}, rx_dataout = {rx_out_wire[7:0]}, rx_deserclock_in = {rx_pll_clkout[3:0]}, rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]}, rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]}, rx_disperr = {wire_receive_pcs0_disperr[0]}, rx_enapatternalign = 1'b0, rx_errdetect = {wire_receive_pcs0_errdetect[0]}, rx_freqlocked = {(rx_freqlocked_wire[0] & (~ rx_analogreset[0]))}, rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked}, rx_locktodata = 1'b0, rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])}, rx_locktorefclk = 1'b0, rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout}, rx_out_wire = {wire_receive_pcs0_dataout[7:0]}, rx_patterndetect = {wire_receive_pcs0_patterndetect[0]}, rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]}, rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout}, rx_phfifordenable = 1'b1, rx_phfiforeset = 1'b0, rx_phfifowrdisable = 1'b0, rx_pldcruclk_in = {rx_cruclk[0]}, rx_pll_clkout = {wire_rx_cdr_pll0_clk}, rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout}, rx_plllocked_wire = {wire_rx_cdr_pll0_locked}, rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0}, rx_pma_clockout = {wire_receive_pma0_clockout}, rx_pma_dataout = {wire_receive_pma0_dataout}, rx_pma_locktorefout = {wire_receive_pma0_locktorefout}, rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]}, rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]}, rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout}, rx_powerdown = 1'b0, rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]}, rx_prbscidenable = 1'b0, rx_recovclkout = {rx_pma_clockout[0]}, rx_rlv = {wire_receive_pcs0_rlv}, rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]}, rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]}, rx_runningdisp = {wire_receive_pcs0_runningdisp[0]}, rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]}, rx_syncstatus = {wire_receive_pcs0_syncstatus[0]}, rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]}, tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]}, tx_clkout = {tx_core_clkout_wire[0]}, tx_clkout_int_wire = {wire_transmit_pcs0_clkout}, tx_core_clkout_wire = {tx_clkout_int_wire[0]}, tx_coreclk_in = {tx_core_clkout_wire[0]}, tx_datain_wire = {tx_datain[7:0]}, tx_dataout = {wire_transmit_pma0_dataout}, tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout}, tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]}, tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]}, tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]}, tx_forcedisp_wire = {1'b0}, tx_invpolarity = 1'b0, tx_localrefclk = {wire_transmit_pma0_clockout}, tx_phfiforeset = 1'b0, tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]}, tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout}, tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout}, tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout}, txdetectrxout = {wire_transmit_pcs0_txdetectrx}, w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout}; endmodule //altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_nmca //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module altera_tse_alt4gxb_gige_wo_rmfifo ( cal_blk_clk, fixedclk, fixedclk_fast, gxb_powerdown, pll_inclk, pll_powerdown, reconfig_clk, reconfig_togxb, rx_analogreset, rx_cruclk, rx_datain, rx_digitalreset, rx_seriallpbken, tx_ctrlenable, tx_datain, tx_digitalreset, pll_locked, reconfig_fromgxb, rx_clkout, rx_ctrldetect, rx_dataout, rx_disperr, rx_errdetect, rx_freqlocked, rx_patterndetect, rx_recovclkout, rx_rlv, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_runningdisp, rx_syncstatus, tx_clkout, tx_dataout)/* synthesis synthesis_clearbox = 2 */; input cal_blk_clk; input fixedclk; input [5:0] fixedclk_fast; input [0:0] gxb_powerdown; input pll_inclk; input [0:0] pll_powerdown; input reconfig_clk; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; input [0:0] rx_cruclk; input [0:0] rx_datain; input [0:0] rx_digitalreset; input [0:0] rx_seriallpbken; input [0:0] tx_ctrlenable; input [7:0] tx_datain; input [0:0] tx_digitalreset; output [0:0] pll_locked; output [16:0] reconfig_fromgxb; output rx_clkout; output [0:0] rx_ctrldetect; output [7:0] rx_dataout; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_freqlocked; output [0:0] rx_patterndetect; output [0:0] rx_recovclkout; output [0:0] rx_rlv; output [0:0] rx_rmfifodatadeleted; output [0:0] rx_rmfifodatainserted; output [0:0] rx_runningdisp; output [0:0] rx_syncstatus; output [0:0] tx_clkout; output [0:0] tx_dataout; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 [0:0] rx_cruclk; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif parameter starting_channel_number = 0; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [16:0] sub_wire2; wire [0:0] sub_wire3; wire [0:0] sub_wire4; wire [0:0] sub_wire5; wire [0:0] sub_wire6; wire [0:0] sub_wire7; wire sub_wire8; wire [7:0] sub_wire9; wire [0:0] sub_wire10; wire [0:0] sub_wire11; wire [0:0] sub_wire12; wire [0:0] sub_wire13; wire [0:0] sub_wire14; wire [0:0] sub_wire15; wire [0:0] sub_wire16; wire [0:0] rx_patterndetect = sub_wire0[0:0]; wire [0:0] pll_locked = sub_wire1[0:0]; wire [16:0] reconfig_fromgxb = sub_wire2[16:0]; wire [0:0] rx_freqlocked = sub_wire3[0:0]; wire [0:0] rx_disperr = sub_wire4[0:0]; wire [0:0] rx_recovclkout = sub_wire5[0:0]; wire [0:0] rx_runningdisp = sub_wire6[0:0]; wire [0:0] rx_syncstatus = sub_wire7[0:0]; wire rx_clkout = sub_wire8; wire [7:0] rx_dataout = sub_wire9[7:0]; wire [0:0] rx_errdetect = sub_wire10[0:0]; wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0]; wire [0:0] rx_rlv = sub_wire12[0:0]; wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0]; wire [0:0] tx_clkout = sub_wire14[0:0]; wire [0:0] tx_dataout = sub_wire15[0:0]; wire [0:0] rx_ctrldetect = sub_wire16[0:0]; altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_nmca altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_nmca_component ( .reconfig_togxb (reconfig_togxb), .cal_blk_clk (cal_blk_clk), .fixedclk (fixedclk), .rx_datain (rx_datain), .rx_digitalreset (rx_digitalreset), .pll_powerdown (pll_powerdown), .tx_datain (tx_datain), .tx_digitalreset (tx_digitalreset), .gxb_powerdown (gxb_powerdown), .rx_cruclk (rx_cruclk), .rx_seriallpbken (rx_seriallpbken), .reconfig_clk (reconfig_clk), .rx_analogreset (rx_analogreset), .fixedclk_fast (fixedclk_fast), .tx_ctrlenable (tx_ctrlenable), .pll_inclk (pll_inclk), .rx_patterndetect (sub_wire0), .pll_locked (sub_wire1), .reconfig_fromgxb (sub_wire2), .rx_freqlocked (sub_wire3), .rx_disperr (sub_wire4), .rx_recovclkout (sub_wire5), .rx_runningdisp (sub_wire6), .rx_syncstatus (sub_wire7), .rx_clkout (sub_wire8), .rx_dataout (sub_wire9), .rx_errdetect (sub_wire10), .rx_rmfifodatainserted (sub_wire11), .rx_rlv (sub_wire12), .rx_rmfifodatadeleted (sub_wire13), .tx_clkout (sub_wire14), .tx_dataout (sub_wire15), .rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2 clearbox_macroname = alt4gxb clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=125.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=slb;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=none;rx_rate_match_pattern1=10100010010101111100; rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=5;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=4;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=1;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=5;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=4;tx_use_external_termination=false;" */; defparam altera_tse_alt4gxb_gige_wo_rmfifo_alt4gxb_nmca_component.starting_channel_number = starting_channel_number; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" // Retrieval info: PRIVATE: IP_MODE STRING "TSE" // Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE" // Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0" // Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC" // Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none" // Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0" // Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0" // Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0" // Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0" // Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0" // Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0" // Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0" // Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None" // Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0" // Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0" // Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps" // Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false" // Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0" // Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0" // Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0" // Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0" // Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0" // Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0" // Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false" // Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO" // Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" // Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2" // Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX" // Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb" // Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb" // Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1" // Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex" // Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0" // Retrieval info: CONSTANT: PROTOCOL STRING "gige" // Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1" // Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10" // Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false" // Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE" // Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v" // Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium" // Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true" // Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32" // Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal" // Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "none" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20" // Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5" // Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true" // Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2" // Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true" // Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true" // Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true" // Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false" // Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false" // Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO" // Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v" // Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High" // Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU" // Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium" // Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true" // Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1" // Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1" // Retrieval info: CONSTANT: number_of_quads NUMERIC "1" // Retrieval info: CONSTANT: reconfig_calibration STRING "true" // Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17" // Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4" // Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5" // Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1" // Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4" // Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1" // Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1" // Retrieval info: CONSTANT: rx_use_external_termination STRING "false" // Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1" // Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1" // Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5" // Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1" // Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4" // Retrieval info: CONSTANT: tx_use_external_termination STRING "false" // Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk" // Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk" // Retrieval info: USED_PORT: fixedclk_fast 0 0 0 0 INPUT NODEFVAL "fixedclk_fast" // Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]" // Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk" // Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]" // Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]" // Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk" // Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]" // Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]" // Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]" // Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout" // Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]" // Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]" // Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]" // Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]" // Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]" // Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]" // Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]" // Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]" // Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]" // Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]" // Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]" // Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]" // Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]" // Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]" // Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]" // Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]" // Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]" // Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]" // Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]" // Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]" // Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0 // Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0 // Retrieval info: CONNECT: @fixedclk_fast 0 0 0 0 fixedclk_fast 0 0 0 0 // Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0 // Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0 // Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0 // Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0 // Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0 // Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0 // Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0 // Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0 // Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0 // Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0 // Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0 // Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0 // Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0 // Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0 // Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0 // Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0 // Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0 // Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0 // Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0 // Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0 // Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0 // Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0 // Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0 // Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0 // Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0 // Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 // Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_wo_rmfifo_bb.v TRUE // Retrieval info: LIB_FILE: stratixiv_hssi
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