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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [verilog/] [top.rtl] - Rev 131
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//=============================================================================
// Rtl Glue Logic
//=============================================================================
assign cpu_pg0_data = pg0_add[0]?mem_rdata[15:8]:mem_rdata[7:0];
assign pg00_ram_rd = pg0_rd||(mem_cs && mem_rd);
assign pg00_ram_l_wr = (pg0_wr||(mem_cs && mem_wr)) && (!pg0_add[0]);
assign pg00_ram_h_wr = (pg0_wr||(mem_cs && mem_wr)) && ( pg0_add[0]);
assign io_module_pic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};
assign io_module_vic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};
cde_sram_dp
#( .WIDTH (8),
.ADDR (7),
.WORDS (128),
.DEFAULT (8'hff))
pg00_ram_l
(
.clk (clk),
.cs (1'b1),
.raddr (pg0_add[7:1]),
.rd (pg00_ram_rd),
.rdata (mem_rdata[7:0]),
.waddr (pg0_add[7:1]),
.wdata (mem_wdata[7:0]),
.wr (pg00_ram_l_wr));
cde_sram_dp
#( .WIDTH (8),
.ADDR (7),
.WORDS (128),
.DEFAULT (8'hff))
pg00_ram_h
(
.clk (clk),
.cs (1'b1),
.raddr (pg0_add[7:1]),
.rd (pg00_ram_rd),
.rdata (mem_rdata[15:8]),
.waddr (pg0_add[7:1]),
.wdata (mem_wdata[15:8]),
.wr (pg00_ram_h_wr));
//=============================================================================
//
//=============================================================================
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