Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>adv_debug_sys</spirit:library>
<spirit:name>adv_dbg_if</spirit:name>
<spirit:version>jtag_i</spirit:version>  <spirit:configuration>default</spirit:configuration>  





<spirit:busInterfaces>

 <spirit:busInterface><spirit:name>jtag</spirit:name>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_rtl"/>
  <spirit:slave/>
    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>test_logic_reset</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rst_i</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort>
        <spirit:name>capture_dr_i</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort>
        <spirit:name>shift_dr_i</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>update_dr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort>
        <spirit:name>update_dr_i</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>tdi_i</spirit:name>
       <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
      </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
      <spirit:logicalPort><spirit:name>tdo</spirit:name>
      </spirit:logicalPort>
      <spirit:physicalPort><spirit:name>tdo_o</spirit:name>
      <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
      </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
      <spirit:logicalPort><spirit:name>select</spirit:name>
      </spirit:logicalPort>
      <spirit:physicalPort><spirit:name>debug_select_i</spirit:name>
      </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
      <spirit:logicalPort><spirit:name>clk</spirit:name>
      </spirit:logicalPort>
      <spirit:physicalPort><spirit:name>tck_i</spirit:name>
      </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>






</spirit:busInterfaces>










<spirit:model>
       <spirit:views>




      </spirit:views>




<spirit:ports>




</spirit:ports>



</spirit:model>












</spirit:component>