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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb_i.xml] - Rev 131

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>adv_debug_sys</spirit:library>
<spirit:name>adv_dbg_if</spirit:name>
<spirit:version>wb_i</spirit:version>  <spirit:configuration>default</spirit:configuration>  





<spirit:busInterfaces>








 <spirit:busInterface><spirit:name>wb_clk</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wb_clk_i</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>wb_reset</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>reset</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wb_rst_i</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>






<spirit:busInterface><spirit:name>wb</spirit:name>
   <spirit:busType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="def"/>
   <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="rtl"/>
   <spirit:master/>
     <spirit:portMaps>

        <spirit:portMap>
         <spirit:logicalPort><spirit:name>adr</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_adr_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>



        <spirit:portMap>
         <spirit:logicalPort><spirit:name>wdata</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_dat_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>rdata</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_dat_i</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>sel</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_sel_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>we</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_we_o</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>cyc</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_cyc_o</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>stb</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_stb_o</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>ack</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_ack_i</spirit:name>
         <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>cab</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_cab_o</spirit:name>
         <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>err</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_err_i</spirit:name>
         <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
         </spirit:physicalPort>
       </spirit:portMap>



        <spirit:portMap>
         <spirit:logicalPort><spirit:name>cti</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_cti_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>2</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>

        <spirit:portMap>
         <spirit:logicalPort><spirit:name>bte</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>wb_bte_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>





     </spirit:portMaps>

</spirit:busInterface>






</spirit:busInterfaces>












<spirit:model>




</spirit:model>












</spirit:component>

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