Subversion Repositories socgen

v 20100214 1
B 300 0  3400 3300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3450   5 10 1 1 0 0 1 1
device=io_ext_mem_interface_def
T 400 3650 5 10 1 1 0 0 1 1
refdes=U?
T 400 3800    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 3800    0 10 0 1 0 0 1 1
library=io
T 400 3800    0 10 0 1 0 0 1 1
component=io_ext_mem_interface
T 400 3800    0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=mem_wdata[15:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=mem_addr[13:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1 
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=ext_rdata[15:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1 
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=addr[3:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=wr
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 300 1600 0 1600 4 0 1  
{
T 400 1600 5 10 1 1 0 1 1 1 
pinnumber=rd
T 400 1600 5 10 0 1 0 1 1 1 
pinseq=8
}
P 300 1800 0 1800 4 0 1  
{
T 400 1800 5 10 1 1 0 1 1 1 
pinnumber=mem_wr
T 400 1800 5 10 0 1 0 1 1 1 
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=mem_rd
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=mem_cs
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 300 2400 0 2400 4 0 1  
{
T 400 2400 5 10 1 1 0 1 1 1 
pinnumber=ext_wait
T 400 2400 5 10 0 1 0 1 1 1 
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=enable
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 300 2800 0 2800 4 0 1  
{
T 400 2800 5 10 1 1 0 1 1 1 
pinnumber=cs
T 400 2800 5 10 0 1 0 1 1 1 
pinseq=14
}
P 300 3000 0 3000 4 0 1  
{
T 400 3000 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 3000 5 10 0 1 0 1 1 1 
pinseq=15
}
P 3700 200 4000 200 10 1 1
{
T 3600 200 5  10 1 1 0 7 1 1 
pinnumber=wait_st[7:0]
T 3600 200 5  10 0 1 0 7 1 1 
pinseq=16
}
P 3700 400 4000 400 10 1 1
{
T 3600 400 5  10 1 1 0 7 1 1 
pinnumber=rdata[7:0]
T 3600 400 5  10 0 1 0 7 1 1 
pinseq=17
}
P 3700 600 4000 600 10 1 1
{
T 3600 600 5  10 1 1 0 7 1 1 
pinnumber=mem_rdata[15:0]
T 3600 600 5  10 0 1 0 7 1 1 
pinseq=18
}
P 3700 800 4000 800 10 1 1
{
T 3600 800 5  10 1 1 0 7 1 1 
pinnumber=ext_wdata[15:0]
T 3600 800 5  10 0 1 0 7 1 1 
pinseq=19
}
P 3700 1000 4000 1000 10 1 1
{
T 3600 1000 5  10 1 1 0 7 1 1 
pinnumber=ext_cs[1:0]
T 3600 1000 5  10 0 1 0 7 1 1 
pinseq=20
}
P 3700 1200 4000 1200 10 1 1
{
T 3600 1200 5  10 1 1 0 7 1 1 
pinnumber=ext_addr[23:0]
T 3600 1200 5  10 0 1 0 7 1 1 
pinseq=21
}
P 3700 1400 4000 1400 10 1 1
{
T 3600 1400 5  10 1 1 0 7 1 1 
pinnumber=ext_add[23:1]
T 3600 1400 5  10 0 1 0 7 1 1 
pinseq=22
}
P 3700 1600 4000 1600 10 1 1
{
T 3600 1600 5  10 1 1 0 7 1 1 
pinnumber=bank[7:0]
T 3600 1600 5  10 0 1 0 7 1 1 
pinseq=23
}
P 3700 1800 4000 1800 4 0 1
{
T 3600 1800 5  10 1 1 0 7 1 1
pinnumber=mem_wait
T 3700 1800 5  10 0 1 0 7 1 1
pinseq=24
}
P 3700 2000 4000 2000 4 0 1
{
T 3600 2000 5  10 1 1 0 7 1 1
pinnumber=ext_wr
T 3700 2000 5  10 0 1 0 7 1 1
pinseq=25
}
P 3700 2200 4000 2200 4 0 1
{
T 3600 2200 5  10 1 1 0 7 1 1
pinnumber=ext_ub
T 3700 2200 5  10 0 1 0 7 1 1
pinseq=26
}
P 3700 2400 4000 2400 4 0 1
{
T 3600 2400 5  10 1 1 0 7 1 1
pinnumber=ext_stb
T 3700 2400 5  10 0 1 0 7 1 1
pinseq=27
}
P 3700 2600 4000 2600 4 0 1
{
T 3600 2600 5  10 1 1 0 7 1 1
pinnumber=ext_rd
T 3700 2600 5  10 0 1 0 7 1 1
pinseq=28
}
P 3700 2800 4000 2800 4 0 1
{
T 3600 2800 5  10 1 1 0 7 1 1
pinnumber=ext_lb
T 3700 2800 5  10 0 1 0 7 1 1
pinseq=29
}