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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [verilog/] [top.mouse.rtl] - Rev 131
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reg wait_n_reg;always@(posedge clk)if(reset || enable)beginwait_n_reg <= 1'b0;endelsewait_n_reg <= 1'b1;assign wait_n = wait_n_reg;