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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [verilog/] [top.body] - Rev 131

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parameter PS2_DATA      = 4'h0;
parameter STATUS        = 4'h2;
parameter CNTRL         = 4'h4;




`VARIANT`MB 
ps2_micro_reg
( 
   .clk                ( clk              ),
   .reset              ( reset            ),
   .enable             ( enable           ),                  
   .cs                 ( cs               ),                  
   .wr                 ( wr               ), 
   .rd                 ( rd               ),
   .addr               ( addr[3:0]        ),
   .byte_lanes         ( 1'b1             ),
   .wdata              ( wdata[7:0]       ),
   .rdata              ( rdata            ),
   .ps2_data_rdata     ( rcv_data         ),
   .ps2_data_dec       ( ps2_data_rd      ),


   .ps2_data_cs    (),
   .wdata_buf_cs (),
   .wdata_buf_dec (),
   .wdata_buf_wr_0 (),
   .status_cs (),
   .status_dec (),
   .cntrl_cs (),
   .cntrl_dec (),
   .cntrl_wr_0 (),


   .status_rdata       ({!buffer_empty   ,
                          rcv_data_avail ,
                          busy           ,
                          rx_parity_error,
                          rx_parity_rcv  ,
                          rx_parity_cal  ,
                          rx_frame_error ,
                          tx_ack_error }  ),
   .cntrl              ( cntrl            ),
   .cntrl_rdata        ( cntrl            ),
   .next_cntrl         ( cntrl            ),
   .wdata_buf          ( wdata_buf        ), 
   .next_wdata_buf     ( wdata_buf        )
);


always@(posedge clk)
if (reset) 
  begin
    ps2_data_read_stb <= 1'b0;
   end
else 
  begin
   ps2_data_read_stb  <= (  enable &&  ps2_data_rd  && rd );
  end





assign   ps2_rx_clear      = cntrl[0] ? read :rd && cs && enable && ps2_data_rd;
assign        poll_enable  =   cntrl[0];

            

  
   


   

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