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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [icarus/] [default/] [test_define] - Rev 131

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reg [31:0] d;

  parameter SPI_TX_0   = 5'h0;
  parameter SPI_CTRL   = 5'h10;
  parameter SPI_DIVIDE = 5'h14;
  parameter SPI_SS     = 5'h18;


initial
 begin
 $display("              ");
 $display("          ===================================================");
 $display("%t  Test Start",$realtime  );
 $display("          ===================================================");
 $display("              ");
 test.cg.next(8);
 
 $display("%t  Out of reset  ",$realtime  );
 test.cg.next(88);


 test.bus16.u_write(24'h004002, 16'h0011);
 test.cg.next(10);
 test.bus16.u_write(24'h004004, 16'h0022);
 test.cg.next(10);
 test.bus16.u_write(24'h004002, 16'h00ff);
 test.cg.next(10);
 test.bus16.u_write(24'h004004, 16'h00aa);
 test.cg.next(10);
 test.bus16.u_write(24'h004024, 16'h000f);
 test.cg.next(10);
 test.bus16.u_write(24'h004028, 16'h000e);
 test.cg.next(10);
 test.bus16.u_write(24'h004044, 16'h000d);
 test.cg.next(10);
 test.bus16.u_write(24'h004048, 16'h000c);
 test.cg.next(10);
 test.bus16.u_write(24'h004060, 16'h000b);
 test.cg.next(10);
 test.bus16.u_write(24'h004062, 16'h000a);
 test.cg.next(10);
 test.bus16.u_write(24'h004064, 16'h0009);
 test.cg.next(10);

 test.bus16.u_cmp(24'h004002, 16'h00ff);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004004, 16'h00aa);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004024, 16'h000f);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004028, 16'h000e);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004044, 16'h000d);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004048, 16'h000c);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004060, 16'h000b);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004062, 16'h000a);
 test.cg.next(10);
 test.bus16.u_cmp(24'h004064, 16'h0009);

 test.cg.next(100);


test.cg.exit;
end









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