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always@(*)
 begin
 if(addr_in[15:8] == 8'h00)     mem_cs         = 1'b1;
 else                            mem_cs         = 1'b0;
 end 

 reg CS0_r;



always@(posedge clk)

begin
     CS0_r  <=     mem_cs;
end 






 reg mem_cs2;
 reg CSP_r;

always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)  mem_cs2         = 1'b1;  
 else                            mem_cs2         = 1'b0;        
 end 

always@(posedge clk)
     begin
     CSP_r  <=     mem_cs2;
     end 





 reg mem_cs3;
 reg CSI_r;   

always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)  mem_cs3         = 1'b1;
 else                            mem_cs3         = 1'b0;
 end 

always@(posedge clk)

begin
     CSI_r  <=    mem_cs3 ;   
end 




 reg mem_cs4;
 reg CSB_r;

   
always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)  mem_cs4          = 1'b1;
 else                            mem_cs4          = 1'b0;
 end

always@(posedge clk)

begin
     CSB_r  <=     mem_cs4;
end 







 reg mem_cs5;
 reg CSE_r;

always@(*)
 begin
 if(addr_in[15:14] == 2'b01)    mem_cs5         = 1'b1;
 else                            mem_cs5         = 1'b0;
 end




always@(posedge clk)

begin
     CSE_r  <=     mem_cs5;
end 







   
   




assign mem_addr   = addr_in;
assign mem_rd     = rd_in;
assign mem_wr     = wr_in;
assign mem_wdata  = {wdata_in,wdata_in};
assign enable     = ~( ext_mem_wait || io_reg_wait  );



reg data_cs_r;

always@(*)
 begin
 if(addr_in[15:12] == 4'b0000)   data_cs           = 1'b1;
 else                            data_cs           = 1'b0;
 end 

always@(posedge clk)

begin
     data_cs_r  <=     data_cs;
end 

assign data_addr            = addr_in[11:1];
assign data_rd              = rd_in;
assign data_wr              = wr_in;
assign data_wdata           = {wdata_in,wdata_in};
assign data_be[0]           = !addr_in[0];
assign data_be[1]           =  addr_in[0];



always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)   io_reg_cs           = 1'b1;
 else                            io_reg_cs           = 1'b0;
 end 
assign io_reg_addr            = addr_in[11:0];
assign io_reg_rd              = rd_in;
assign io_reg_wr              = wr_in;
assign io_reg_wdata           = wdata_in;


always@(*)
 begin
 if(addr_in[15:14] == 2'b01)     ext_mem_cs            = 1'b1;
 else                            ext_mem_cs            = 1'b0;
 end

assign ext_mem_addr            = addr_in[13:0];
assign ext_mem_rd              = rd_in;
assign ext_mem_wr              = wr_in;
assign ext_mem_wdata           = {wdata_in,wdata_in};




always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)   prog_rom_mem_cs          = 1'b1;
 else                            prog_rom_mem_cs          = 1'b0;
 end


assign prog_rom_mem_addr            = addr_in[11:0];
assign prog_rom_mem_rd              = rd_in;
assign prog_rom_mem_wr              = wr_in;
assign prog_rom_mem_wdata           = {wdata_in,wdata_in};



always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)  sh_prog_rom_mem_cs         = 1'b1;  
 else                           sh_prog_rom_mem_cs         = 1'b0;        
 end 


assign sh_prog_rom_mem_addr            = addr_in[11:0];
assign sh_prog_rom_mem_rd              = rd_in;
assign sh_prog_rom_mem_wr              = wr_in;
assign sh_prog_rom_mem_wdata           = {wdata_in,wdata_in};




always@(*)
if ( CS0_r )       rdata_out = mem_rdata;
else
if ( data_cs_r )   rdata_out = data_rdata;
else
if ( CSB_r )       rdata_out = prog_rom_mem_rdata;
else
if ( CSI_r )       rdata_out = io_reg_rdata;
else
if ( CSP_r )       rdata_out = sh_prog_rom_mem_rdata;
else               rdata_out = ext_mem_rdata;