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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [spi_interface/] [sim/] [testbenches/] [xml/] [spi_interface_def_duth.design.xml] - Rev 135
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component spi_interface -version def //
// //
-->
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>logic</ipxact:library>
<ipxact:name>spi_interface</ipxact:name>
<ipxact:version>def_duth.design</ipxact:version>
<ipxact:adHocConnections>
<ipxact:adHocConnection>
<ipxact:name>busy</ipxact:name>
<ipxact:externalPortReference portRef="busy" />
<ipxact:internalPortReference componentRef="dut" portRef="busy" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>clk</ipxact:name>
<ipxact:externalPortReference portRef="clk" />
<ipxact:internalPortReference componentRef="dut" portRef="clk" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>spi_clk_pad_in</ipxact:name>
<ipxact:externalPortReference portRef="spi_clk_pad_in" />
<ipxact:internalPortReference componentRef="dut" portRef="spi_clk_pad_in" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>spi_mosi_pad_in</ipxact:name>
<ipxact:externalPortReference portRef="spi_mosi_pad_in" />
<ipxact:internalPortReference componentRef="dut" portRef="spi_mosi_pad_in" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>spi_miso_pad_out</ipxact:name>
<ipxact:externalPortReference portRef="spi_miso_pad_out" />
<ipxact:internalPortReference componentRef="dut" portRef="spi_miso_pad_out" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>spi_sel_n_pad_in</ipxact:name>
<ipxact:externalPortReference portRef="spi_sle_n_pad_in" />
<ipxact:internalPortReference componentRef="dut" portRef="spi_sel_n_pad_in" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>reset</ipxact:name>
<ipxact:externalPortReference portRef="reset" />
<ipxact:internalPortReference componentRef="dut" portRef="reset" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>rx_data</ipxact:name>
<ipxact:externalPortReference portRef="rx_data" left="15" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="rx_data" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>tx_data</ipxact:name>
<ipxact:externalPortReference portRef="tx_data" left="15" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="tx_data" />
</ipxact:adHocConnection>
</ipxact:adHocConnections>
<ipxact:componentInstances>
<ipxact:componentInstance>
<ipxact:instanceName>dut</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="logic" name="spi_interface" version="def" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="FREQ">FREQ</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
</ipxact:componentInstances>
</ipxact:design>